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Author	SHA1	Message	Date
MaxP	ff7782fd91	Refines VHDL formatting and counter logic ... Aligns signal and port declarations for improved readability. Adjusts horizontal and vertical counter bit-width calculations for accuracy. Splits conditional statements across multiple lines for better clarity. No functional changes introduced.	2025-04-16 17:29:41 +00:00
MaxP	cd6524c62e	Test @ 640x480	2025-03-27 16:01:32 +00:00
MaxP	c449016835	Add VGA Timing Generator implementation and testbench files ... Test @ 1080P	2025-03-27 16:00:08 +00:00
MaxP	860108547f	Add project configuration and VHDL language server settings	2025-03-27 15:59:53 +00:00
MaxP	70df56addc	Add .gitignore to exclude locale files	2025-03-27 15:59:31 +00:00
MaxP	1873eafba8	Add submodule for Xilinx ISE Makefile	2025-03-27 15:59:05 +00:00