This website requires JavaScript.
Explore
Help
Sign In
HDL
/
VGA
Watch
1
Star
0
Fork
0
You've already forked VGA
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
4
Commits
1
Branch
0
Tags
c4490168350b5fa44c02ff42ee2091f73700ba58
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
MaxP
c449016835
Add VGA Timing Generator implementation and testbench files
...
Test @ 1080P
2025-03-27 16:00:08 +00:00
build
@
54949f43c0
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
src
Add VGA Timing Generator implementation and testbench files
2025-03-27 16:00:08 +00:00
tests
Add VGA Timing Generator implementation and testbench files
2025-03-27 16:00:08 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-03-27 15:59:31 +00:00
.gitmodules
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
project.cfg
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
vhdl_ls.toml
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
Description
No description provided
60
KiB
Languages
VHDL
100%
