HDL/VGA
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add submodule for Xilinx ISE Makefile

Browse Source
This commit is contained in:
0xMax42
2025-03-27 15:59:05 +00:00
commit 1873eafba8
2 changed files with 4 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
.gitmodules vendored Normal file
View File

@@ -0,0 +1,3 @@
[submodule "build"]
path = build
url = https://github.com/PxaMMaxP/Xilinx-ISE-Makefile.git

1
build Submodule

Submodule build added at 54949f43c0