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86c1f6d6a7
feat(devcontainer): update GPG agent socket mapping
main
Max P
2025-04-28 15:27:19 +00:00
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1ab18cda83
feat(devcontainer): update image source and post-start setup
Max P
2025-04-28 15:26:22 +00:00
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1011989322
Adds project configuration file for VGA design with Xilinx ISE settings
Max P
2025-04-27 19:27:56 +00:00
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1c700b8703
Adds initial devcontainer configuration for Xilinx ISE 14.7
Max P
2025-04-27 19:27:50 +00:00
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5d93242fe4
Updates .gitignore to include additional build and output directories
Max P
2025-04-27 19:27:01 +00:00
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5b901c0dcf
Removes unused submodule and associated build directory
Max P
2025-04-27 19:26:55 +00:00
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a73f125357
Refactors VGA timing and mode handling
Max P
2025-04-26 10:26:52 +00:00
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319b51bf56
Consolidates VGA output signals into a single pixel bus
Max P
2025-04-25 16:07:57 +00:00
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50f36afcf4
Adds VGA controller and testbench enhancements
Max P
2025-04-25 15:59:37 +00:00
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167901eaa6
Misc
Max P
2025-04-25 15:59:15 +00:00
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ff7782fd91
Refines VHDL formatting and counter logic
MaxP
2025-04-16 17:29:41 +00:00
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cd6524c62e
Test @ 640x480
MaxP
2025-03-27 16:01:32 +00:00
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c449016835
Add VGA Timing Generator implementation and testbench files
MaxP
2025-03-27 16:00:08 +00:00
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860108547f
Add project configuration and VHDL language server settings
MaxP
2025-03-27 15:59:53 +00:00
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70df56addc
Add .gitignore to exclude locale files
MaxP
2025-03-27 15:59:31 +00:00
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1873eafba8
Add submodule for Xilinx ISE Makefile
MaxP
2025-03-27 15:59:05 +00:00