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cd6524c62e93e2a6d51418c15586fa8b372a8e61
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MaxP
cd6524c62e
Test @ 640x480
2025-03-27 16:01:32 +00:00
build
@
54949f43c0
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
src
Test @ 640x480
2025-03-27 16:01:32 +00:00
tests
Add VGA Timing Generator implementation and testbench files
2025-03-27 16:00:08 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-03-27 15:59:31 +00:00
.gitmodules
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
project.cfg
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
vhdl_ls.toml
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
Description
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60
KiB
Languages
VHDL
100%
