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ff7782fd91f89f46b4a648631c65a8d09cbab491
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MaxP ff7782fd91 Refines VHDL formatting and counter logic 
Aligns signal and port declarations for improved readability.
Adjusts horizontal and vertical counter bit-width calculations for accuracy.
Splits conditional statements across multiple lines for better clarity.

No functional changes introduced.
2025-04-16 17:29:41 +00:00
build @ 54949f43c0
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
src
Refines VHDL formatting and counter logic
2025-04-16 17:29:41 +00:00
tests
Add VGA Timing Generator implementation and testbench files
2025-03-27 16:00:08 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-03-27 15:59:31 +00:00
.gitmodules
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
project.cfg
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
Description
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60 KiB
Languages
VHDL 100%