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860108547fe2ad6cd4225447c5808068ecf76275
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MaxP
860108547f
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
build
@
54949f43c0
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-03-27 15:59:31 +00:00
.gitmodules
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
project.cfg
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
vhdl_ls.toml
Add project configuration and VHDL language server settings
2025-03-27 15:59:53 +00:00
Description
No description provided
60
KiB
Languages
VHDL
100%
