- Introduces a VHDL implementation for a reorder buffer (ROB)
- Adds generic parameters for slot depth, ID width, and data width
- Implements synchronous reset, clock enable, and data flow logic
- Improves modularity with pipeline stage instantiation
- Introduces a devcontainer setup for Xilinx ISE 14.7
- Configures remote user, workspace, and extensions
- Adds custom VS Code settings and post-start commands
- Improves development environment portability and consistency