Max P 880526968f feat(src): define clock constraints in ROB.ucf ...

- Adds clock net mapping and timing specifications
- Defines a 200 MHz clock period with 50% duty cycle

2025-07-07 13:15:01 +00:00

.devcontainer

feat(devcontainer): add Xilinx ISE development configuration

2025-07-07 13:14:09 +00:00

.vscode

feat(devcontainer): add Xilinx ISE development configuration

2025-07-07 13:14:09 +00:00

src

feat(src): define clock constraints in ROB.ucf

2025-07-07 13:15:01 +00:00

.gitignore

chore(gitignore): add entries for build and config files

2025-07-07 13:14:18 +00:00

project.yml

feat(project): add initial configuration for build and synthesis

2025-07-07 13:14:40 +00:00

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35 KiB

Languages

VHDL 100%