Max P dce101dfdf feat(rob): add reorder buffer entity with slot management ...

- Introduces a VHDL implementation for a reorder buffer (ROB)
- Adds generic parameters for slot depth, ID width, and data width
- Implements synchronous reset, clock enable, and data flow logic
- Improves modularity with pipeline stage instantiation

2025-07-07 13:14:53 +00:00

.devcontainer

feat(devcontainer): add Xilinx ISE development configuration

2025-07-07 13:14:09 +00:00

.vscode

feat(devcontainer): add Xilinx ISE development configuration

2025-07-07 13:14:09 +00:00

src

feat(rob): add reorder buffer entity with slot management

2025-07-07 13:14:53 +00:00

.gitignore

chore(gitignore): add entries for build and config files

2025-07-07 13:14:18 +00:00

project.yml

feat(project): add initial configuration for build and synthesis

2025-07-07 13:14:40 +00:00

Description

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32 KiB

Languages

VHDL 100%