Max P d953462d1f feat(project): add initial configuration for build and synthesis ...

- Introduces project configuration file for FPGA synthesis workflow
- Specifies tool options, sources, constraints, and dependencies
- Enhances customization for optimization and synthesis settings

2025-07-07 13:14:40 +00:00

.devcontainer

feat(devcontainer): add Xilinx ISE development configuration

2025-07-07 13:14:09 +00:00

.vscode

feat(devcontainer): add Xilinx ISE development configuration

2025-07-07 13:14:09 +00:00

.gitignore

chore(gitignore): add entries for build and config files

2025-07-07 13:14:18 +00:00

project.yml

feat(project): add initial configuration for build and synthesis

2025-07-07 13:14:40 +00:00

Description

No description provided

32 KiB

Languages

VHDL 100%