Bumped Makefile version to 1.1.5 and ensured REPORT_DIR is created before generating synthesis reports, addressing the potential issue where missing report directory could disrupt the build process.
- Modified the echo command in the trace target to display the correct path of the Timing Report within the REPORT_DIR, enhancing accuracy in log messages.
- Added "reports/" directory to .gitignore to exclude it from version control.
- Incremented Makefile version from 1.1.3 to 1.1.4.
- Introduced REPORT_DIR variable in Makefile to manage report files.
- Modified ISIM_CMD in Makefile to remove specific commands, simplifying the simulation process.
- Enhanced the clean target in Makefile to also remove the REPORT_DIR, ensuring a clean state for new builds.
- Updated project build process in Makefile to create and use REPORT_DIR for storing synthesis, map, place and route, pinout, and timing reports, improving organization and accessibility of build reports.
* Update Makefile for ISIM test enhancements and version bump
**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master)
Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.
* Update Makefile to version 1.1.1
* Updated Makefile for consistent build output paths and dynamic project references
Enhanced the Makefile to use a centralized `BUILD_DIR` variable for executable paths, increasing consistency across the build process. Adjusted the project reference generation to dynamically pair test files with their respective libraries, ensuring a more accurate and maintainable build configuration. This change streamlines the build workflow and mitigates potential errors due to path mismatches or hard-coded library links.
* Add copy feature
* Add a comprehensive sample configuration file for the project
This commit adds a sample configuration file for the project. It includes main settings such as the project name, target device, and path to the Xilinx ISE installation. It also provides options for source files, test files, ISE executable settings, and programmer settings. This sample configuration file serves as a template for users to customize their project settings.
Improved the build directory management by introducing a new variable `BUILD_DIR`, set to `working`, for a more flexible directory handling. This change ensures that all build artifacts are now generated in a designated directory, which can be easily modified. Adjusted relative paths reference this new directory, ensuring compatibility with the updated structure. The version bump to 1.0.3 reflects these enhancements and potential future improvements in the build process.
- Upgraded Makefile to version 1.0.1, indicating minor revisions or fixes.
- Corrected whitespace inconsistency in MAP_OPTS definition for cleaner code formatting.
- Added reference to the GitHub repository in the header comments for better discoverability of the source.
Refined the Makefile to accommodate pre-programming commands with `PROGRAMMER_PRE` variable and introduced a specific index for flashing with Digilent devices using `DJTG_FLASH_INDEX`. This allows for more flexible configuration pre-programming hooks and coherent handling of different indices for programming and flashing operations.
The README has been updated for clarity and to reflect new options. Simplified the installation instructions for GNU Make, enriched the project configuration section with default values for build options, introduced library naming for Verilog sources, and added a section detailing console output for easy report access post-build. Additionally, documented the new `make flash` target for Digilent programmers and the placeholder for `PROGRAMMER_PRE`.
Updated Makefile to include detailed placement and routing by adding the `-detail` flag to PAR_OPTS. Also increased verbosity levels for tracing by setting TRACE_OPTS to `-v 3 -n 3`, providing more comprehensive diagnostic information during builds.
Refactored the Makefile to allow for dynamic library and filepath resolutions for VHDL and Verilog sources, promoting a more modular project structure. Removed hardcoded library names and filepaths, and replaced them with a mechanism that processes source file definitions, supporting a colon-separated format for specifying libraries and paths.
- Simplified RUN command echo statements for clarity.
- Established functions to process VHDL and Verilog sources, handling omitted library paths and defaults to 'work'.
- Updated build rules to utilize new lists of processed source paths and libraries.
- Included generation of detailed synthesis, map, PAR, pinout, and timing summary reports after relevant build steps for enhanced build insight.
- Modified programming commands to ensure automation without manual intervention by using `sudo` and automating confirmation prompts where applicable.
- Added a new 'flash' target for the Digilent programmer, enabling FPGA flash memory programming.
