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Feature/add testbench simulation support (#2)

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* Update Makefile for ISIM test enhancements and version bump

**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master)

Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.

* Update Makefile to version 1.1.1

* Updated Makefile for consistent build output paths and dynamic project references

Enhanced the Makefile to use a centralized `BUILD_DIR` variable for executable paths, increasing consistency across the build process. Adjusted the project reference generation to dynamically pair test files with their respective libraries, ensuring a more accurate and maintainable build configuration. This change streamlines the build workflow and mitigates potential errors due to path mismatches or hard-coded library links.

* Add copy feature

* Add a comprehensive sample configuration file for the project

This commit adds a sample configuration file for the project. It includes main settings such as the project name, target device, and path to the Xilinx ISE installation. It also provides options for source files, test files, ISE executable settings, and programmer settings. This sample configuration file serves as a template for users to customize their project settings.
This commit is contained in:
Max P
2024-03-24 21:30:17 +01:00
committed by GitHub
parent d7eebb6517
commit c661c3f453
2 changed files with 148 additions and 16 deletions
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54
Makefile
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@@ -12,7 +12,7 @@
# Version
###########################################################################
Makefile_Version := 1.0.3
Makefile_Version := 1.1.3
$(info ISE Makefile Version: $(Makefile_Version))
###########################################################################
@@ -50,6 +50,9 @@ PAR_OPTS ?=
BITGEN_OPTS ?=
TRACE_OPTS ?= -v 3 -n 3
FUSE_OPTS ?= -incremental
ISIM_OPTS ?= -gui
ISIM_CMD ?= vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun all\nvcd dumpflush\nquit
PROGRAMMER ?= none
PROGRAMMER_PRE ?=
@@ -114,6 +117,24 @@ $(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
# Run the function for Verilog sources
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
## Tests
# Initialize the libs and paths variables for VHDL and Verilog testbenches
VHD_TEST_PATHS ?=
VHD_TEST_LIBS ?=
V_TEST_PATHS ?=
V_TEST_LIBS ?=
# Run the function for VHDL tests
$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
# Run the function for Verilog tests
$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
# Get the test names..
TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
###########################################################################
# Default build
###########################################################################
@@ -133,8 +154,8 @@ $(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
$(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
@cp $(BUILD_DIR)/$(PROJECT).prj $@
@$(foreach file,$(VTEST),echo "verilog work \"../../$(file)\"" >> $@;)
@$(foreach file,$(VHDTEST),echo "vhdl work \"../../$(file)\"" >> $@;)
@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
$(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
@@ -176,7 +197,9 @@ $(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR
@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT)_pad.txt\e[m\n"
copy: $(BITFILE)
@cp $(BITFILE) $(COPY_TARGET_DIR)/$(PROJECT).bit
@echo "\n\e[1;32m= Copy bitfile successful =\e[m\n"
###########################################################################
# Testing (work in progress)
@@ -189,24 +212,23 @@ trace: ../project.cfg $(BITFILE)
@echo "\e[1;97m===== Timing Summary Report ======\e[m"
@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
test: $(TEST_EXES)
test: buildtest runtest
$(BUILD_DIR)/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) $(BUILD_DIR)/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
runtest: ${TEST_NAMES}
${TEST_NAMES}:
@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
buildtest: ${TEST_EXES}
$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
-prj $(PROJECT)_sim.prj \
-o isim_$*$(EXE) \
work.$* work.glbl
isim: $(BUILD_DIR)/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
isimgui: $(BUILD_DIR)/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
###########################################################################
# Programming