From c661c3f4536cecbaf8c2dfbb3989c0d878e20f62 Mon Sep 17 00:00:00 2001
From: Max P <46793832+PxaMMaxP@users.noreply.github.com>
Date: Sun, 24 Mar 2024 21:30:17 +0100
Subject: [PATCH] Feature/add testbench simulation support (#2)

* Update Makefile for ISIM test enhancements and version bump

**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master)

Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.

* Update Makefile to version 1.1.1

* Updated Makefile for consistent build output paths and dynamic project references

Enhanced the Makefile to use a centralized `BUILD_DIR` variable for executable paths, increasing consistency across the build process. Adjusted the project reference generation to dynamically pair test files with their respective libraries, ensuring a more accurate and maintainable build configuration. This change streamlines the build workflow and mitigates potential errors due to path mismatches or hard-coded library links.

* Add copy feature

* Add a comprehensive sample configuration file for the project

This commit adds a sample configuration file for the project. It includes main settings such as the project name, target device, and path to the Xilinx ISE installation. It also provides options for source files, test files, ISE executable settings, and programmer settings. This sample configuration file serves as a template for users to customize their project settings.
---
 Makefile           |  54 +++++++++++++++-------
 project.cfg.sample | 110 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 148 insertions(+), 16 deletions(-)
 create mode 100644 project.cfg.sample

diff --git a/Makefile b/Makefile
index e391390..bb3205a 100644
--- a/Makefile
+++ b/Makefile
@@ -12,7 +12,7 @@
 # Version
 ###########################################################################
 
-Makefile_Version := 1.0.3
+Makefile_Version := 1.1.3
 $(info ISE Makefile Version: $(Makefile_Version))
 
 ###########################################################################
@@ -50,6 +50,9 @@ PAR_OPTS         ?=
 BITGEN_OPTS      ?=
 TRACE_OPTS       ?= -v 3 -n 3
 FUSE_OPTS        ?= -incremental
+
+ISIM_OPTS		 ?= -gui
+ISIM_CMD		 ?= vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun all\nvcd dumpflush\nquit
  
 PROGRAMMER       ?= none
 PROGRAMMER_PRE   ?=
@@ -114,6 +117,24 @@ $(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
 # Run the function for Verilog sources
 $(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
 
+## Tests
+
+# Initialize the libs and paths variables for VHDL and Verilog testbenches
+VHD_TEST_PATHS ?=
+VHD_TEST_LIBS  ?=
+V_TEST_PATHS   ?=
+V_TEST_LIBS    ?=
+
+# Run the function for VHDL tests
+$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
+# Run the function for Verilog tests
+$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
+
+# Get the test names..
+TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
+TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
+TEST_EXES = $(foreach test,$(TEST_NAMES),$(BUILD_DIR)/isim_$(test)$(EXE))
+
 ###########################################################################
 # Default build
 ###########################################################################
@@ -133,8 +154,8 @@ $(BUILD_DIR)/$(PROJECT).prj: ../project.cfg
 
 $(BUILD_DIR)/$(PROJECT)_sim.prj: $(BUILD_DIR)/$(PROJECT).prj
 	@cp $(BUILD_DIR)/$(PROJECT).prj $@
-	@$(foreach file,$(VTEST),echo "verilog work \"../../$(file)\"" >> $@;)
-	@$(foreach file,$(VHDTEST),echo "vhdl work \"../../$(file)\"" >> $@;)
+	@$(foreach idx,$(shell seq 1 $(words $(V_TEST_PATHS))),echo "verilog $(word $(idx),$(V_TEST_LIBS)) \"../$(word $(idx),$(V_TEST_PATHS))\"" >> $@;)
+	@$(foreach idx,$(shell seq 1 $(words $(VHD_TEST_PATHS))),echo "vhdl $(word $(idx),$(VHD_TEST_LIBS)) \"../$(word $(idx),$(VHD_TEST_PATHS))\"" >> $@;)
 	@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
 
 $(BUILD_DIR)/$(PROJECT).scr: ../project.cfg
@@ -176,7 +197,9 @@ $(BITFILE): ../project.cfg $(V_PATHS) $(VHD_PATHS) ../$(CONSTRAINTS) $(BUILD_DIR
 	@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
 	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT)_pad.txt\e[m\n"
 	
-
+copy: $(BITFILE)
+	@cp $(BITFILE) $(COPY_TARGET_DIR)/$(PROJECT).bit
+	@echo "\n\e[1;32m= Copy bitfile successful =\e[m\n"
 
 ###########################################################################
 # Testing (work in progress)
@@ -189,24 +212,23 @@ trace: ../project.cfg $(BITFILE)
 	@echo "\e[1;97m===== Timing Summary Report ======\e[m"
 	@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
 
-test: $(TEST_EXES)
+test: buildtest runtest
 
-$(BUILD_DIR)/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) $(BUILD_DIR)/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
+runtest: ${TEST_NAMES}
+
+${TEST_NAMES}:
+	@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$@.cmd
+	@echo "$(ISIM_CMD)" >> $(BUILD_DIR)/isim_$@.cmd
+	cd $(BUILD_DIR) ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
+
+buildtest: ${TEST_EXES}
+
+$(BUILD_DIR)/isim_%$(EXE): $(BUILD_DIR)/$(PROJECT)_sim.prj $(V_PATHS) $(VHD_PATHS) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
 	$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
 	    -prj $(PROJECT)_sim.prj \
 	    -o isim_$*$(EXE) \
 	    work.$* work.glbl
 
-isim: $(BUILD_DIR)/isim_$(TB)$(EXE)
-	@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
-	@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
-	cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
-
-isimgui: $(BUILD_DIR)/isim_$(TB)$(EXE)
-	@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
-	@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
-	cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
-
 
 ###########################################################################
 # Programming
diff --git a/project.cfg.sample b/project.cfg.sample
new file mode 100644
index 0000000..30df022
--- /dev/null
+++ b/project.cfg.sample
@@ -0,0 +1,110 @@
+## Main settings.. ##
+
+# Project name
+# @remark The name of the project is used as default name for the top module and the ucf file
+PROJECT = 
+
+# Target device
+# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
+TARGET_PART = 
+
+# Path to the Xilinx ISE installation
+XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
+
+# Optional the name of the top module (default is the project name)
+# TOPLEVEL = 
+
+# Optional the path/name of the ucf file (default is the project name)
+# CONSTRAINTS = 
+
+# Optional a target to copy the bit file to (make copy)
+# COPY_TARGET_DIR = 
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## Source files settings.. ##
+# The source files to be compiled
+# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
+# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
+
+
+## Test files settings.. ##
+# The testbench files to be compiled
+# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
+# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
+
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## ISE executable settings.. ##
+
+# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
+# COMMON_OPTS = 
+
+# Options for the XST synthesizer
+# @example -register_balancing (yes|no)
+# @example -opt_mode (speed|area)
+# @example -opt_level (1|2)
+XST_OPTS = 
+
+# Options for the NGDBuild tool
+# NGDBUILD_OPTS =
+
+# Options for the MAP tool
+# @example -mt 2 (multi-threading with 2 threads)
+# @example -cm speed (speed optimization)
+# @example -ol high
+# @example -detail
+# @example -timing
+MAP_OPTS = 
+
+# Options for the PAR tool
+# @example -mt 2 (multi-threading with 2 threads)
+# @example -ol high
+PAR_OPTS = 
+
+# Options for the BitGen tool
+# @example -g Compress (compress bitstream)
+# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
+# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
+BITGEN_OPTS = -g StartupClk:JtagClk
+
+# Options for the Trace tool
+# TRACE_OPTS = 
+
+# Options for the Fuse tool
+# FUSE_OPTS = 
+
+# Options for the ISim simulator
+# @example -gui (start the simulator in GUI mode)
+# ISIM_OPTS =
+
+# Options for the ISim batch file
+# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run all \n vcd dumpflush \n quit
+# ISIM_CMD =
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## Programmer settings.. ##
+
+# The programmer to use
+# @example impact | digilent | xc3sprog
+# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
+PROGRAMMER = 
+
+## Digilent JTAG cable settings
+
+# @remark Use the `djtgcfg enum` command to list all available devices
+# DJTG_DEVICE = DOnbUsb
+
+# The index of the JTAG device for the `prog` target
+# DJTG_INDEX = 0
+
+# The index of the flash device for the `flash` target
+# DJTG_FLASH_INDEX = 1
+
+## ## ## ## ## ## ## ##
+# ---------------------
\ No newline at end of file