Max P
4893f9cf7c
Refined the Makefile to accommodate pre-programming commands with `PROGRAMMER_PRE` variable and introduced a specific index for flashing with Digilent devices using `DJTG_FLASH_INDEX`. This allows for more flexible configuration pre-programming hooks and coherent handling of different indices for programming and flashing operations. The README has been updated for clarity and to reflect new options. Simplified the installation instructions for GNU Make, enriched the project configuration section with default values for build options, introduced library naming for Verilog sources, and added a section detailing console output for easy report access post-build. Additionally, documented the new `make flash` target for Digilent programmers and the placeholder for `PROGRAMMER_PRE`.
242 lines
7.7 KiB
Makefile
242 lines
7.7 KiB
Makefile
###########################################################################
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## Xilinx ISE Makefile
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##
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## To the extent possible under law, the author(s) have dedicated all copyright
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## and related and neighboring rights to this software to the public domain
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## worldwide. This software is distributed without any warranty.
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###########################################################################
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###########################################################################
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# Version
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###########################################################################
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Makefile_Version := 1.0.0
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$(info ISE Makefile Version: $(Makefile_Version))
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###########################################################################
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# Include project configuration
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###########################################################################
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include project.cfg
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###########################################################################
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# Default values
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###########################################################################
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ifndef XILINX
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$(error XILINX must be defined)
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endif
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ifndef PROJECT
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$(error PROJECT must be defined)
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endif
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ifndef TARGET_PART
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$(error TARGET_PART must be defined)
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endif
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TOPLEVEL ?= $(PROJECT)
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CONSTRAINTS ?= $(PROJECT).ucf
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BITFILE ?= build/$(PROJECT).bit
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COMMON_OPTS ?= -intstyle xflow
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XST_OPTS ?=
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NGDBUILD_OPTS ?=
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MAP_OPTS ?= -detail
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?= -v 3 -n 3
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FUSE_OPTS ?= -incremental
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PROGRAMMER ?= none
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PROGRAMMER_PRE ?=
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IMPACT_OPTS ?= -batch impact.cmd
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DJTG_EXE ?= djtgcfg
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DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
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DJTG_INDEX ?= 0
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DJTG_FLASH_INDEX ?= 1
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XC3SPROG_EXE ?= xc3sprog
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XC3SPROG_CABLE ?= none
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XC3SPROG_OPTS ?=
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###########################################################################
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# Internal variables, platform-specific definitions, and macros
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###########################################################################
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ifeq ($(OS),Windows_NT)
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XILINX := $(shell cygpath -m $(XILINX))
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CYG_XILINX := $(shell cygpath $(XILINX))
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EXE := .exe
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XILINX_PLATFORM ?= nt64
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PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
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else
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EXE :=
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XILINX_PLATFORM ?= lin64
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PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
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endif
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TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
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RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
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cd build && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
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# isim executables don't work without this
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export XILINX
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# Initialize the libs and paths variables for VHDL and Verilog sources
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VHD_PATHS ?=
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VHD_LIBS ?=
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V_PATHS ?=
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V_LIBS ?=
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# Define a function to process source files
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define process_sources
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$(foreach src,$(1),\
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$(eval lib_and_path=$(subst :, ,$(src))) \
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$(eval libname=$(word 1,$(lib_and_path))) \
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$(eval filepath=$(word 2,$(lib_and_path))) \
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$(if $(filepath),,$(eval filepath=$(libname)) $(eval libname=work)) \
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$(eval $(2) += $(libname)) \
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$(eval $(3) += $(filepath)) \
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)
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endef
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# Run the function for VHDL sources
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$(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
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# Run the function for Verilog sources
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$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
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###########################################################################
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# Default build
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###########################################################################
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default: $(BITFILE)
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clean:
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rm -rf build
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build/$(PROJECT).prj: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@rm -f $@
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@$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
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@$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
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build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
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@cp build/$(PROJECT).prj $@
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@$(foreach file,$(VTEST),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDTEST),echo "vhdl work \"../$(file)\"" >> $@;)
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@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
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build/$(PROJECT).scr: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@rm -f $@
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@echo "run" \
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"-ifn $(PROJECT).prj" \
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"-ofn $(PROJECT).ngc" \
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"-ifmt mixed" \
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"$(XST_OPTS)" \
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"-top $(TOPLEVEL)" \
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"-ofmt NGC" \
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"-p $(TARGET_PART)" \
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> build/$(PROJECT).scr
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$(BITFILE): project.cfg $(V_PATHS) $(VHD_PATHS) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
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@mkdir -p build
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$(call RUN,xst) $(COMMON_OPTS) \
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-ifn $(PROJECT).scr
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$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
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-p $(TARGET_PART) -uc ../$(CONSTRAINTS) \
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$(PROJECT).ngc $(PROJECT).ngd
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$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
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-p $(TARGET_PART) \
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-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
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$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
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-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
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$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
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-w $(PROJECT).ncd $(PROJECT).bit
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@echo "\e[1;32m============ OK ============\e[m\n\n"
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@echo "\e[1;33m============ Reports.. ===========\e[m\n"
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@echo "\e[1;97m==== Synthesis Summary Report ====\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).srp\e[m\n"
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@echo "\e[1;97m======= Map Summary Report =======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).map.mrp\e[m\n"
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@echo "\e[1;97m======= PAR Summary Report =======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).par\e[m\n"
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@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT)_pad.txt\e[m\n"
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###########################################################################
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# Testing (work in progress)
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###########################################################################
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trace: project.cfg $(BITFILE)
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$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
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$(PROJECT).ncd $(PROJECT).pcf
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@echo "\n\e[1;33m============ Reports.. ===========\e[m\n"
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@echo "\e[1;97m===== Timing Summary Report ======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).twr\e[m\n"
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test: $(TEST_EXES)
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build/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) build/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
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$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
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-prj $(PROJECT)_sim.prj \
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-o isim_$*$(EXE) \
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work.$* work.glbl
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isim: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
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isimgui: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
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###########################################################################
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# Programming
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###########################################################################
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ifeq ($(PROGRAMMER), impact)
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prog: $(BITFILE)
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$(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
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endif
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ifeq ($(PROGRAMMER), digilent)
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prog: $(BITFILE)
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$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), xc3sprog)
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prog: $(BITFILE)
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$(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), none)
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prog:
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$(error PROGRAMMER must be set to use 'make prog')
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endif
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###########################################################################
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# Flash
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###########################################################################
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ifeq ($(PROGRAMMER), digilent)
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flash: $(BITFILE)
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$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
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endif
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###########################################################################
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