Major rework - separate config from Makefile; add README

Makefile

@@ -1,36 +1,48 @@
-## Uncomment these lines and set them appropriately.
+## Xilinx ISE Makefile
+##
+## To the extent possible under law, the author(s) have dedicated all copyright
+## and related and neighboring rights to this software to the public domain
+## worldwide. This software is distributed without any warranty.
 
-#PROJECT = <project name>
-#TOPLEVEL = <top-level module name>
-#CONSTRAINTS = <constraints file name>.ucf
-#TARGET_PART = <part name, e.g. xc6slx9-2-tqg144>
+include project.cfg
 
+ifndef XILINX
+    $(error XILINX must be defined)
+endif
 
-## Where are the Xilinx tools installed?
+ifndef PROJECT
+    $(error PROJECT must be defined)
+endif
 
-#(Linux) XILINX = /opt/xilinx/14.7/ISE_DS/ISE/bin/lin
-#(Windows) XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
+ifndef TARGET_PART
+    $(error TARGET_PART must be defined)
+endif
 
+TOPLEVEL        ?= $(PROJECT)
+CONSTRAINTS     ?= $(PROJECT).ucf
+BITFILE         ?= build/$(PROJECT).bit
 
-## What are your HDL source files? Repeat this line for each file.
+COMMON_OPTS     ?= -intstyle xflow
+XST_OPTS        ?=
+NGDBUILD_OPTS   ?=
+MAP_OPTS        ?=
+PAR_OPTS        ?=
+BITGEN_OPTS     ?=
 
-#VSOURCE += example.v
+PROGRAMMER      ?= none
 
+IMPACT_OPTS     ?= -batch impact.cmd
 
-## These settings are probably fine for most projects.
-
-COMMON_OPTS = -intstyle xflow
-NGDBUILD_OPTS =
-MAP_OPTS = -mt 2
-PAR_OPTS = -mt 2
-TRCE_OPTS = -e
-BITGEN_OPTS = -g Compress
+DJTG_EXE        ?= djtgcfg
+DJTG_DEVICE     ?= DJTG_DEVICE-NOT-SET
+DJTG_INDEX      ?= 0
 
+XC3SPROG_EXE    ?= xc3sprog
+XC3SPROG_CABLE  ?= -c none
+XC3SPROG_OPTS   ?=
 
 ###########################################################################
 
-BITFILE = build/$(PROJECT).bit
-
 RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
 	cd build && $(XILINX)/$(1)
 
@@ -39,13 +51,14 @@ default: $(BITFILE)
 clean:
 	rm -rf build
 
-build/$(PROJECT).prj: Makefile
+build/$(PROJECT).prj: project.cfg
 	@echo "Updating $@"
 	@mkdir -p build
 	@rm -f $@
 	@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
+	@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
 
-build/$(PROJECT).scr: Makefile
+build/$(PROJECT).scr: project.cfg
 	@echo "Updating $@"
 	@mkdir -p build
 	@rm -f $@
@@ -53,12 +66,13 @@ build/$(PROJECT).scr: Makefile
 	    "-ifn $(PROJECT).prj" \
 	    "-ofn $(PROJECT).ngc" \
 	    "-ifmt mixed" \
+	    "$(XST_OPTS)" \
 	    "-top $(TOPLEVEL)" \
 	    "-ofmt NGC" \
 	    "-p $(TARGET_PART)" \
 	    > build/$(PROJECT).scr
 
-$(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
+$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
 	@mkdir -p build
 	$(call RUN,xst) $(COMMON_OPTS) \
 	    -ifn $(PROJECT).scr
@@ -74,16 +88,24 @@ $(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJ
 	    -w $(PROJECT).ncd $(PROJECT).bit
 	@echo -ne "\e[1;32m======== OK ========\e[m\n"
 
-## You'll need to write an impact.cmd if you want to use this part.
-## A simple one looks like:
-##
-##    setMode -bscan
-##    setCable -p auto
-##    addDevice -p 1 -file build/projectname.bit
-##    program -p 1
-##    quit
-##
-## You may need to change this rule to something else entirely if your board
-## doesn't support Impact.
+ifeq ($(PROGRAMMER), impact)
 prog: $(BITFILE)
-	$(XILINX)/impact -batch impact.cmd
+	$(XILINX)/impact -batch $(IMPACT_OPTS)
+endif
+
+ifeq ($(PROGRAMMER), digilent)
+prog: $(BITFILE)
+	$(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
+endif
+
+ifeq ($(PROGRAMMER), xc3sprog)
+prog: $(BITFILE)
+	$(XC3SPROG_EXE) $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
+endif
+
+ifeq ($(PROGRAMMER), none)
+prog:
+	$(error PROGRAMMER must be set to use 'make prog')
+endif
+
+# vim: set filetype=make: #