simplify! no more Perl requirement

2016-01-09 16:10:13 -08:00
parent bf40a125cf
commit f99254bdc2
5 changed files with 72 additions and 133 deletions
--- a/129
+++ b/129
@@ -1,74 +1,89 @@
-XILINX = /cygdrive/c/Xilinx/14.4/ISE_DS/ISE/bin/nt64
+## Uncomment these lines and set them appropriately.

-XST = $(XILINX)/xst
-NGDBUILD = $(XILINX)/ngdbuild
-MAP = $(XILINX)/map
-PAR = $(XILINX)/par
-BITGEN = $(XILINX)/bitgen
-PERL = perl
+#PROJECT = <project name>
+#TOPLEVEL = <top-level module name>
+#CONSTRAINTS = <constraints file name>.ucf
+#TARGET_PART = <part name, e.g. xc6slx9-2-tqg144>

-DIGILENT_DEVICE_NAME = Nexys2

-FPGA_PART = xc3s1200e-fg320-4
+## Where are the Xilinx tools installed?

-BITFILE = blinky.bit
-TOPMODULE = toplevel
-VSOURCES = toplevel.v
-CONSTRAINTS = nexys2.ucf
+#(Linux) XILINX = /opt/xilinx/14.7/ISE_DS/ISE/bin/lin
+#(Windows) XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64

-BITGEN_OPTS += -g UnusedPin:Pullnone
-BITGEN_OPTS += -g StartupClk:JtagClk
-BITGEN_OPTS += -g Compress

-##############################################################################
+## What are your HDL source files? Repeat this line for each file.

-COMMON_OPTS += -intstyle xflow
-RUNNING = echo -e "\n\n\e[1;35m>>>> Running $(1)\e[m"
+#VSOURCE += example.v
+
+
+## These settings are probably fine for most projects.
+
+COMMON_OPTS = -intstyle xflow
+NGDBUILD_OPTS =
+MAP_OPTS = -mt 2
+PAR_OPTS = -mt 2
+TRCE_OPTS = -e
+BITGEN_OPTS = -g Compress
+
+
+###########################################################################
+
+BITFILE = build/$(PROJECT).bit
+
+RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
+	cd build && $(XILINX)/$(1)

 default: $(BITFILE)

 clean:
-	rm -rf build/
+	rm -rf build

-prog: $(BITFILE)
-	djtgcfg -d $(DIGILENT_DEVICE_NAME) -i 0 -f $(BITFILE) prog
+build/$(PROJECT).prj: Makefile
+	@echo "Updating $@"
+	@mkdir -p build
+	@rm -f $@
+	@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)

-build/project.prj: Makefile
-	test -d build || mkdir build
-	$(PERL) generate_project.pl build/project.prj $(addprefix ../src/,$(VSOURCES))
-
-build/project.scr: Makefile
-	test -d build || mkdir build
-	$(PERL) generate_script.pl build/project.scr \
-	    "-ifn project.prj" \
+build/$(PROJECT).scr: Makefile
+	@echo "Updating $@"
+	@mkdir -p build
+	@rm -f $@
+	@echo "run" \
+	    "-ifn $(PROJECT).prj" \
+	    "-ofn $(PROJECT).ngc" \
 	    "-ifmt mixed" \
-	    "-top $(TOPMODULE)" \
-	    "-ofn project.ngc" \
+	    "-top $(TOPLEVEL)" \
 	    "-ofmt NGC" \
-	    "-p $(FPGA_PART)"
+	    "-p $(TARGET_PART)" \
+	    > build/$(PROJECT).scr

-build/project.ngc: build/project.prj build/project.scr $(addprefix src/,$(VSOURCES))
-	@touch build/stamp.ngc ; $(call RUNNING,Xst)
-	cd build ; $(XST) $(COMMON_OPTS) $(XST_OPTS) -ifn project.scr
-	@test build/project.ngc -nt build/stamp.ngc
-
-build/project.ngd: build/project.ngc src/$(CONSTRAINTS)
-	@touch build/stamp.ngd ; $(call RUNNING,ngdbuild)
-	cd build ; $(NGDBUILD) $(COMMON_OPTS) $(NGD_OPTS) -p $(FPGA_PART) -uc ../src/$(CONSTRAINTS) project.ngc project.ngd
-	@test build/project.ngd -nt build/stamp.ngd
-
-build/project.map.ncd build/project.pcf: build/project.ngd
-	@touch build/stamp.map ; $(call RUNNING,map)
-	cd build ; $(MAP) $(COMMON_OPTS) $(MAP_OPTS) -p $(FPGA_PART) -o project.map.ncd project.ngd project.pcf
-	@test build/project.map.ncd -nt build/stamp.map
-
-build/project.par.ncd: build/project.map.ncd build/project.pcf
-	@touch build/stamp.par ; $(call RUNNING,PAR)
-	cd build ; $(PAR) $(COMMON_OPTS) $(PAR_OPTS) -w project.map.ncd project.par.ncd project.pcf
-	@test build/project.par.ncd -nt build/stamp.par
-
-$(BITFILE): build/project.par.ncd
-	@touch build/stamp.bit ; $(call RUNNING,bitgen)
-	cd build ; $(BITGEN) $(COMMON_OPTS) $(BITGEN_OPTS) -w project.par.ncd $(BITFILE) && mv $(BITFILE) ..
-	@test $(BITFILE) -nt build/stamp.bit
+$(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
+	@mkdir -p build
+	$(call RUN,xst) $(COMMON_OPTS) \
+	    -ifn $(PROJECT).scr
+	$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
+	    -p $(TARGET_PART) -uc ../$(CONSTRAINTS) \
+	    $(PROJECT).ngc $(PROJECT).ngd
+	$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
+	    -p $(TARGET_PART) \
+	    -w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
+	$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
+	    -w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
+	$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
+	    -w $(PROJECT).ncd $(PROJECT).bit
+	@echo -ne "\e[1;32m======== OK ========\e[m\n"

+## You'll need to write an impact.cmd if you want to use this part.
+## A simple one looks like:
+##
+##    setMode -bscan
+##    setCable -p auto
+##    addDevice -p 1 -file build/projectname.bit
+##    program -p 1
+##    quit
+##
+## You may need to change this rule to something else entirely if your board
+## doesn't support Impact.
+prog: $(BITFILE)
+	$(XILINX)/impact -batch impact.cmd
--- a/generate_project.pl
+++ b/generate_project.pl
@@ -1,13 +0,0 @@
-#!/usr/bin/perl
-use strict;
-my $prjfile = shift or die "Usage: $0 project.prj [source...]\n";
-open my $prj, ">", $prjfile or die "$prjfile: $!";
-for my $source (@ARGV) {
-    if ($source =~ m{\.v$}) {
-        print $prj "verilog work $source\n";
-    } elsif ($source =~ m{\.vhd}) {
-        print $prj "vhdl work $source\n";
-    } else {
-        die "unknown source type '$source'\n";
-    }
-}
--- a/generate_script.pl
+++ b/generate_script.pl
@@ -1,8 +0,0 @@
-#!/usr/bin/perl
-use strict;
-my $scrfile = shift or die "Usage: $0 project.prj [source...]\n";
-open my $scr, ">", $scrfile or die "$scrfile: $!\n";
-print $scr "run\n";
-for my $arg (@ARGV) {
-    print $scr "$arg\n";
-}
--- a/src/nexys2.ucf
+++ b/src/nexys2.ucf
@@ -1,34 +0,0 @@
-## Clocks
-
-NET "clk"   LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
-
-
-## Buttons
-
-#NET "btn0" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
-#NET "btn1" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
-#NET "btn2" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
-#NET "btn3" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
-
-
-## Switches
-
-NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
-NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
-NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
-NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
-NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
-NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
-NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
-NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
-
-## LEDs
-
-NET "led<0>"  LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
-NET "led<1>"  LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
-NET "led<2>"  LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
-NET "led<3>"  LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
-NET "led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
-NET "led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
-NET "led<6>" LOC = "E4";  # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
-NET "led<7>" LOC = "P4";  # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
--- a/src/toplevel.v
+++ b/src/toplevel.v
@@ -1,21 +0,0 @@
-`timescale 1ns / 1ps
-
-module toplevel(
-    input clk,
-    input  [7:0] sw,
-    output [7:0] led
-);
-
-    reg [23:0] ctr;
-    reg [7:0] state;
-
-    always @(posedge clk) begin
-        ctr <= ctr + 1;
-        if (ctr == 0) begin
-            state <= state + sw;
-        end
-    end
-
-    assign led = state;
-
-endmodule