Files
Xilinx-ISE-Build/generate_project.pl
2015-06-24 10:26:44 -07:00

14 lines
391 B
Perl

#!/usr/bin/perl
use strict;
my $prjfile = shift or die "Usage: $0 project.prj [source...]\n";
open my $prj, ">", $prjfile or die "$prjfile: $!";
for my $source (@ARGV) {
if ($source =~ m{\.v$}) {
print $prj "verilog work $source\n";
} elsif ($source =~ m{\.vhd}) {
print $prj "vhdl work $source\n";
} else {
die "unknown source type '$source'\n";
}
}