From 2654cb829e1e9cddfeaa1dc0d422cbc149cbd5f0 Mon Sep 17 00:00:00 2001 From: Dusk Date: Sat, 14 May 2016 23:56:36 -0700 Subject: [PATCH] Major rework - separate config from Makefile; add README --- LICENSE => LICENSE.md | 0 Makefile | 92 ++++++++++++++--------- README.md | 170 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+), 35 deletions(-) rename LICENSE => LICENSE.md (100%) create mode 100644 README.md diff --git a/LICENSE b/LICENSE.md similarity index 100% rename from LICENSE rename to LICENSE.md diff --git a/Makefile b/Makefile index 011c5f9..aa95ffa 100644 --- a/Makefile +++ b/Makefile @@ -1,36 +1,48 @@ -## Uncomment these lines and set them appropriately. +## Xilinx ISE Makefile +## +## To the extent possible under law, the author(s) have dedicated all copyright +## and related and neighboring rights to this software to the public domain +## worldwide. This software is distributed without any warranty. -#PROJECT = -#TOPLEVEL = -#CONSTRAINTS = .ucf -#TARGET_PART = +include project.cfg +ifndef XILINX + $(error XILINX must be defined) +endif -## Where are the Xilinx tools installed? +ifndef PROJECT + $(error PROJECT must be defined) +endif -#(Linux) XILINX = /opt/xilinx/14.7/ISE_DS/ISE/bin/lin -#(Windows) XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64 +ifndef TARGET_PART + $(error TARGET_PART must be defined) +endif +TOPLEVEL ?= $(PROJECT) +CONSTRAINTS ?= $(PROJECT).ucf +BITFILE ?= build/$(PROJECT).bit -## What are your HDL source files? Repeat this line for each file. +COMMON_OPTS ?= -intstyle xflow +XST_OPTS ?= +NGDBUILD_OPTS ?= +MAP_OPTS ?= +PAR_OPTS ?= +BITGEN_OPTS ?= -#VSOURCE += example.v +PROGRAMMER ?= none +IMPACT_OPTS ?= -batch impact.cmd -## These settings are probably fine for most projects. - -COMMON_OPTS = -intstyle xflow -NGDBUILD_OPTS = -MAP_OPTS = -mt 2 -PAR_OPTS = -mt 2 -TRCE_OPTS = -e -BITGEN_OPTS = -g Compress +DJTG_EXE ?= djtgcfg +DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET +DJTG_INDEX ?= 0 +XC3SPROG_EXE ?= xc3sprog +XC3SPROG_CABLE ?= -c none +XC3SPROG_OPTS ?= ########################################################################### -BITFILE = build/$(PROJECT).bit - RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \ cd build && $(XILINX)/$(1) @@ -39,13 +51,14 @@ default: $(BITFILE) clean: rm -rf build -build/$(PROJECT).prj: Makefile +build/$(PROJECT).prj: project.cfg @echo "Updating $@" @mkdir -p build @rm -f $@ @$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;) + @$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;) -build/$(PROJECT).scr: Makefile +build/$(PROJECT).scr: project.cfg @echo "Updating $@" @mkdir -p build @rm -f $@ @@ -53,12 +66,13 @@ build/$(PROJECT).scr: Makefile "-ifn $(PROJECT).prj" \ "-ofn $(PROJECT).ngc" \ "-ifmt mixed" \ + "$(XST_OPTS)" \ "-top $(TOPLEVEL)" \ "-ofmt NGC" \ "-p $(TARGET_PART)" \ > build/$(PROJECT).scr -$(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr +$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr @mkdir -p build $(call RUN,xst) $(COMMON_OPTS) \ -ifn $(PROJECT).scr @@ -74,16 +88,24 @@ $(BITFILE): Makefile $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJ -w $(PROJECT).ncd $(PROJECT).bit @echo -ne "\e[1;32m======== OK ========\e[m\n" -## You'll need to write an impact.cmd if you want to use this part. -## A simple one looks like: -## -## setMode -bscan -## setCable -p auto -## addDevice -p 1 -file build/projectname.bit -## program -p 1 -## quit -## -## You may need to change this rule to something else entirely if your board -## doesn't support Impact. +ifeq ($(PROGRAMMER), impact) prog: $(BITFILE) - $(XILINX)/impact -batch impact.cmd + $(XILINX)/impact -batch $(IMPACT_OPTS) +endif + +ifeq ($(PROGRAMMER), digilent) +prog: $(BITFILE) + $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE) +endif + +ifeq ($(PROGRAMMER), xc3sprog) +prog: $(BITFILE) + $(XC3SPROG_EXE) $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE) +endif + +ifeq ($(PROGRAMMER), none) +prog: + $(error PROGRAMMER must be set to use 'make prog') +endif + +# vim: set filetype=make: # diff --git a/README.md b/README.md new file mode 100644 index 0000000..4e50610 --- /dev/null +++ b/README.md @@ -0,0 +1,170 @@ +Xilinx ISE Makefile +=================== + +Tired of clicking around in Xilinx ISE? Run your builds from the command line! + + +Requirements +------------ + + * Xilinx ISE, ideally 14.7 (the final version) + + * GNU (or compatible?) Make + + Install this through Cygwin on Windows. + + +Creating a project +------------------ + +To start building a project, you will need to create a file `project.cfg` in +the top level of your project. This file is a text file sourced by Make, so +it consists of `KEY = value` pairs. It must define at least the following keys: + + * `PROJECT` + + The name of the project, used as a name for certain intermediate files, and + as the default name for the top-level module and constraints file. + + * `TARGET_PART` + + The full part-speed-package identifier for the Xilinx part to be targeted, + e.g. `xc6slx9-2-tqg144`. + + * `XILINX` + + The path to the appropriate binaries directory of the target Xilinx ISE + install, e.g. + `/cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64` + or + `/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64` + for typical installs. + + * `VSOURCE` and/or `VHDSOURCE` + + The space-separated names of all Verilog and/or VHDL source files to be + used in the project. + + You can define these on multiple lines using `+=`, e.g. + + VSOURCE += foo.v + VSOURCE += bar.v + +A simple `project.cfg` may thus resemble: + + PROJECT = example + TARGET_PART = xc6slx9-2-cpg196 + + XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64 + + VSOURCE = example.v + +A number of other keys can be set in the project configuration, including: + + * `TOPLEVEL` + + The name of the top-level module to be used in the project. + (Defaults to `$PROJECT`.) + + * `CONSTRAINTS` + + The name of the constraints file (`.ucf`) to be used for the project. + (Defaults to `$PROJECT.ucf`.) + + * `COMMON_OPTS` + + Extra command-line options to be passed to all ISE executables. Defaults to + `-intstyle xflow`. + + * `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS` + + Extra command-line options to be passed to the corresponding ISE tools. All + default to empty. + + Note that `XST_OPTS` will not appear on the command line during + compilation, as the XST options are embedded in a script file. + + `MAP_OPTS` and `PAR_OPTS` can be set to `-mt 2` to use multithreading, + which may speed up compilation of large designs. + + `BITGEN_OPTS` can be set to `-g Compress` to apply bitstream compression. + + * `PROGRAMMER` + + The name of the programmer to be used for `make prog`. Currently supported + values are: + + * `impact` + + Uses Xilinx iMPACT for programming, using a batch file named + `impact.cmd` by default. The iMPACT command line may be overridden by + setting `IMPACT_OPTS`. + + A typical batch file may resemble: + + setMode -bscan + setCable -p auto + addDevice -p 1 -file build/projectname.bit + program -p 1 + quit + + * `djtg` + + Uses the Digilent JTAG utility for programming, which must be installed + separately. The name of the board must be set as `DJTG_DEVICE`; the + path to the djtgcfg executable can be set as `DJTG_EXE`, and the index + of the device can be set as `DJTG_INDEX`. + + * `xc3sprog` + + Uses the xc3sprog utility for programming, which must also be installed + separately. The cable name must be set as `XC3SPROG_CABLE`; additional + options can be set as `XC3SPROG_OPTS`. + + +Targets +------- + +The Xilinx ISE Makefile implements the following targets: + + * `make default` (or just `make`) + + Builds the bitstream. + + * `make clean` + + Removes the build directory. + + * `make prog` + + Writes the bitstream to a target device. Requires some additional + configuration; see below for details. + + +Unimplemented features +---------------------- + +The following features are not currently implemented. (Pull requests are +encouraged!) + + * Building and/or running testbenches + + * Generation of SPI or other unusual programming files + + * CPLD synthesis + + * Synthesis tools other than XST + + * Display and/or handling of warnings and errors from `build/_xmsgs` + + * Anything else (open an issue?) + + +License +------- + +To the extent possible under law, the author(s) have dedicated all copyright +and related and neighboring rights to this software to the public domain +worldwide. This software is distributed without any warranty. + +See LICENSE.md for details.