canonical XILINX path; initial testbench support
This commit is contained in:
Dusk
83
Makefile
83
Makefile
@@ -1,11 +1,18 @@
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###########################################################################
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## Xilinx ISE Makefile
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##
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## To the extent possible under law, the author(s) have dedicated all copyright
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## and related and neighboring rights to this software to the public domain
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## worldwide. This software is distributed without any warranty.
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###########################################################################
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include project.cfg
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###########################################################################
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# Default values
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###########################################################################
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ifndef XILINX
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$(error XILINX must be defined)
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endif
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@@ -28,6 +35,8 @@ NGDBUILD_OPTS ?=
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MAP_OPTS ?=
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?=
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FUSE_OPTS ?= -incremental
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PROGRAMMER ?= none
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@@ -38,13 +47,39 @@ DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
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DJTG_INDEX ?= 0
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XC3SPROG_EXE ?= xc3sprog
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XC3SPROG_CABLE ?= -c none
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XC3SPROG_CABLE ?= none
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XC3SPROG_OPTS ?=
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###########################################################################
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# Internal variables, platform-specific definitions, and macros
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###########################################################################
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ifeq ($(OS),Windows_NT)
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XILINX := $(shell cygpath -m $(XILINX))
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CYG_XILINX := $(shell cygpath $(XILINX))
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EXE := .exe
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XILINX_PLATFORM ?= nt64
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PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
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else
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EXE :=
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XILINX_PLATFORM ?= lin64
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PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
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endif
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TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
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RUN = @echo -ne "\n\n\e[1;33m======== $(1) ========\e[m\n\n"; \
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cd build && $(XILINX)/$(1)
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cd build && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
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# isim executables don't work without this
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export XILINX
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###########################################################################
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# Default build
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###########################################################################
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default: $(BITFILE)
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@@ -58,6 +93,12 @@ build/$(PROJECT).prj: project.cfg
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@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
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build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
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@cp build/$(PROJECT).prj $@
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@$(foreach file,$(VTEST),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDTEST),echo "vhdl work \"../$(file)\"" >> $@;)
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@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
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build/$(PROJECT).scr: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@@ -88,6 +129,39 @@ $(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(P
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-w $(PROJECT).ncd $(PROJECT).bit
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@echo -ne "\e[1;32m======== OK ========\e[m\n"
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###########################################################################
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# Testing (work in progress)
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###########################################################################
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trace: project.cfg $(BITFILE)
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$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
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$(PROJECT).ncd $(PROJECT).pcf
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test: $(TEST_EXES)
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build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST)
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$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
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-prj $(PROJECT)_sim.prj \
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-o isim_$*$(EXE) \
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work.$* work.glbl
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#FIXME TB ?= $(error Must set TB to name of a testbench module)
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isim: build/isim_$(TB)$(EXE)
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
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isimgui: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
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###########################################################################
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# Programming
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###########################################################################
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ifeq ($(PROGRAMMER), impact)
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prog: $(BITFILE)
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$(XILINX)/impact -batch $(IMPACT_OPTS)
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@@ -100,7 +174,7 @@ endif
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ifeq ($(PROGRAMMER), xc3sprog)
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prog: $(BITFILE)
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$(XC3SPROG_EXE) $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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$(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), none)
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@@ -108,4 +182,7 @@ prog:
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$(error PROGRAMMER must be set to use 'make prog')
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endif
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###########################################################################
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# vim: set filetype=make: #
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22
README.md
22
README.md
@@ -35,9 +35,9 @@ it consists of `KEY = value` pairs. It must define at least the following keys:
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The path to the appropriate binaries directory of the target Xilinx ISE
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install, e.g.
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`/cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64`
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`/cygdrive/c/Xilinx/14.7/ISE_DS/ISE`
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or
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`/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64`
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`/opt/Xilinx/14.7/ISE_DS/ISE`
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for typical installs.
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* `VSOURCE` and/or `VHDSOURCE`
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@@ -61,6 +61,13 @@ A simple `project.cfg` may thus resemble:
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A number of other keys can be set in the project configuration, including:
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* `XILINX_PLATFORM`
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The Xilinx name for the platform to build for, e.g. `nt64` or `lin`.
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`nt64` is used by default for Windows systems, and `lin64` for Linux
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systems, so you only need to set this if you explicitly need to use the
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32-bit version of the tools for some reason.
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* `TOPLEVEL`
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The name of the top-level module to be used in the project.
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@@ -76,7 +83,8 @@ A number of other keys can be set in the project configuration, including:
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Extra command-line options to be passed to all ISE executables. Defaults to
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`-intstyle xflow`.
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* `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`
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* `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`,
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`TRACE_OPTS`, `FUSE_OPTS`
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Extra command-line options to be passed to the corresponding ISE tools. All
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default to empty.
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@@ -141,14 +149,18 @@ The Xilinx ISE Makefile implements the following targets:
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configuration; see below for details.
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Running unit tests
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------------------
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is a work in progress.
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Unimplemented features
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----------------------
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The following features are not currently implemented. (Pull requests are
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encouraged!)
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* Building and/or running testbenches
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* Generation of SPI or other unusual programming files
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* CPLD synthesis
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