Adjusts entity and architecture formatting for consistency, aligning spacing and indentation across declarations and constants.
Adds `O_MUX_Select` output signal to indicate routing decision, improving functionality and clarity of the module.
Introduces the PipelineSwitch component with configurable routing behavior based on input comparison modes. Implements modes such as "none", "or", "and", "xor", "equal", and others. Adds a comprehensive testbench to validate functionality across all supported modes.
Implements a pipeline buffer component supporting passthrough and register modes, controlled via a dedicated controller.
Adds AXI-like handshake signals for data flow management.
Includes a testbench to validate functionality with randomized delays.
Addresses robust data buffering and flow control.
Refactors pipeline architecture by separating input and output stages.
Introduces additional controllers and registers for better modularity.
Aligns signal and attribute formatting for improved readability.
Introduces a comprehensive VHDL testbench for the PipelineFilter entity, covering various mask modes ("none", "or", "and", "xor", "equal", "not_equal").
Includes signal setup, instance mapping, and test cases to validate filtering behavior for each mode.
Ensures correct functionality and highlights potential errors during simulation.
Updates random seed values and adjusts pipeline configuration constants for improved testing flexibility. Refactors write and read processes for clarity, adding additional checks and error handling. Introduces `stop` function to terminate simulation on critical errors.
Enhances test coverage and simulation reliability.
Implements a generic VHDL entity for data filtering based on a bitmask and comparison modes.
Supports configurable filtering modes such as 'none', 'or', 'and', 'xor', 'equal', and 'not_equal'.
Integrates AXI-like valid/ready handshake for synchronous data transfer.
Ensures proper handling of unrecognized modes and validates mask size at runtime.
Introduces a VHDL entity for a configurable pipeline stage with generic parameters for data widths, reset behavior, and register balancing. Implements AXI-like handshake interfaces for input and output data management. Includes support for up to four data channels with optional pipeline registers.
Facilitates modular and reusable design for pipeline processing.
Introduces conditional logic to handle cases with zero pipeline stages, improving adaptability.
Adds default values for generics and ports to enhance usability and reduce configuration errors.
Cleans up formatting for better readability and maintainability.
Relates to improved design modularity.
Enhanced the PipelineController's validity logic to handle single-stage configurations properly. This update ensures that the validity bit is correctly updated for systems that operate with only one pipeline stage, addressing a potential logic flaw in previous versions. Additionally, clarified documentation for random number generation in pipeline testbench.
- Introduce comprehensive documentation for Pipeline Controller and Register, detailing core functions, generics, ports, and processes. Focus on data flow control, validity control, adjustability, and register rebalancing mechanisms.
- Implement AXI-Like handshaking in Pipeline Controller for improved input and output data handling, supporting active-high ready and valid signals for efficient data transfer.
- Refine Pipeline Register with register rebalancing options (no, yes, forward, backward) to optimize combinatorial logic pipelining in synthesis, configurable via `G_RegisterBalancing` generic.
- Update generics and ports descriptions to reflect the inclusion of I/O FFs in pipeline depth calculation and clarify the reset active level and handshaking protocol.
- Extend VHDL source for both modules to embody described functionalities and adjustments, ensuring alignment with documentation enhancements.
- Augment testbench `Pipeline_tb.vhd` with random intervals for write and read operations, emphasizing dynamic testing scenarios.
