Adds configurable pipeline stage module
Introduces a VHDL entity for a configurable pipeline stage with generic parameters for data widths, reset behavior, and register balancing. Implements AXI-like handshake interfaces for input and output data management. Includes support for up to four data channels with optional pipeline registers. Facilitates modular and reusable design for pipeline processing.
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src/PipelineStage.vhd
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161
src/PipelineStage.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity PipelineStage is
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generic (
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--@ Number of pipeline stages (FFs in the pipeline including I/O FFs)
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G_PipelineStages : integer := 3;
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--@ Data width
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G_D0_Width : integer := 1;
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--@ Data width
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G_D1_Width : integer := 0;
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--@ Data width
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G_D2_Width : integer := 0;
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--@ Data width
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G_D3_Width : integer := 0;
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--@ Reset active at this level
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G_ResetActiveAt : std_logic := '1';
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--@ Register balancing attribute
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--@ - `no` : **Disable** register balancing,
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--@ - `yes`: **Enable** register balancing in both directions,
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--@ - `forward`: **Enable** register balancing
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--@ and moves a set of FFs at the inputs of a LUT to a single FF at its output,
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--@ - `backward`: **Enable** register balancing
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--@ and moves a single FF at the output of a LUT to a set of FFs at its inputs.
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G_RegisterBalancing : string := "yes"
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);
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port (
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--@ Clock; (**Rising edge** triggered)
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I_CLK : in std_logic := '0';
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--@ Clock Enable; (**Synchronous**, **Active high**)
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I_CE : in std_logic := '1';
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--@ Reset; (**Synchronous**, **Active high**)
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I_RST : in std_logic := '0';
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--@ Pipeline enable for additional stages; (**Synchronous**, **Active high**)
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O_PipelineEnable : out std_logic := '0';
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--@ @virtualbus AXI-Data-In @dir In Input interface with AXI-like handshake
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--@ AXI like valid; (**Synchronous**, **Active high**)
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I_Valid : in std_logic := '0';
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--@ AXI like ready; (**Synchronous**, **Active high**)
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O_Ready : out std_logic := '0';
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--@ Data input 0
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I_Data_0 : in std_logic_vector(G_D0_Width - 1 downto 0) := (others => '-');
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--@ Data input 1
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I_Data_1 : in std_logic_vector(G_D1_Width - 1 downto 0) := (others => '-');
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--@ Data input 2
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I_Data_2 : in std_logic_vector(G_D2_Width - 1 downto 0) := (others => '-');
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--@ Data input 3
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I_Data_3 : in std_logic_vector(G_D3_Width - 1 downto 0) := (others => '-');
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--@ @end
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--@ @virtualbus AXI-Data-Out @dir Out Output interface with AXI-like handshake
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--@ AXI like valid; (**Synchronous**, **Active high**)
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O_Valid : out std_logic := '0';
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--@ AXI like ready; (**Synchronous**, **Active high**)
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I_Ready : in std_logic := '0';
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--@ Data output 0
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O_Data_0 : out std_logic_vector(G_D0_Width - 1 downto 0) := (others => '-');
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--@ Data output 1
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O_Data_1 : out std_logic_vector(G_D1_Width - 1 downto 0) := (others => '-');
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--@ Data output 2
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O_Data_2 : out std_logic_vector(G_D2_Width - 1 downto 0) := (others => '-');
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--@ Data output 3
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O_Data_3 : out std_logic_vector(G_D3_Width - 1 downto 0) := (others => '-')
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--@ @end
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);
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end entity PipelineStage;
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architecture Rtl of PipelineStage is
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signal S_PipelineEnable : std_logic := '0';
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begin
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--@ Forwarding the pipeline enable signal to the output port.
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--@ This signal is used to control the pipeline enable signal
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--@ of additional external stages.
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O_PipelineEnable <= S_PipelineEnable;
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--@ Pipeline controller
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I_PipelineCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_ResetActiveAt => G_ResetActiveAt
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_PipelineEnable,
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I_Valid => I_Valid,
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O_Ready => O_Ready,
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O_Valid => O_Valid,
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I_Ready => I_Ready
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);
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GEN_PipelineRegister_D0 : if G_D0_Width > 0 generate
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--@ Pipeline register Data 0
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I_PielineRegister_D0 : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_D0_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_PipelineEnable,
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I_Data => I_Data_0,
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O_Data => O_Data_0
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);
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end generate;
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GEN_PipelineRegister_D1 : if G_D1_Width > 0 generate
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--@ Pipeline register Data 1
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I_PielineRegister_D1 : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_D1_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_PipelineEnable,
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I_Data => I_Data_1,
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O_Data => O_Data_1
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);
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end generate;
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GEN_PipelineRegister_D2 : if G_D2_Width > 0 generate
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--@ Pipeline register Data 2
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I_PielineRegister_D2 : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_D2_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_PipelineEnable,
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I_Data => I_Data_2,
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O_Data => O_Data_2
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);
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end generate;
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GEN_PipelineRegister_D3 : if G_D3_Width > 0 generate
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--@ Pipeline register Data 3
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I_PielineRegister_D3 : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_D3_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_PipelineEnable,
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I_Data => I_Data_3,
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O_Data => O_Data_3
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);
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end generate;
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end architecture;
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