Add the documentation to the readme file.
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README.md
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See at docs subdirectory for the documentation..
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# Entity: PipelineController
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- **File**: PipelineController.vhd
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## Diagram
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## Description
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- Name: **Pipeline Controller**
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- Version: 0.0.1
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- Author: _Maximilian Passarello ([Blog](mpassarello.de))_
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- License: [MIT](LICENSE)
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The Pipeline Controller provides an easy way to construct a pipeline
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with AXI-Like handshaking at the input and output of the pipeline.
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### Core functions
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- **Data flow control**: Data flow control is implemented via handshaking at the input and output ports.
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- **Validity control**: The controller keeps the validity of the data in the individual pipeline stages under control.
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- **Adjustability**: The pipeline controller can be customized via the generics.
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### Generics
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Use the generic `G_PipelineStages` to set how deep the pipeline is.
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This depth contains all the registers associated with the pipeline.
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For example, for an _I_FF ⇨ Combinatorics ⇨ O_FF_ construction, the generic must be set to **2**.
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The active level of the reset input can also be set.
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### Clock Enable
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The `I_CE` port is active high and, when deactivated,
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effectively switches on the acceptance or output of data via handshaking in addition to the pipeline.
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### Reset
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A reset is explicitly **not** necessary on the pipeline registers.
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The validity of the data is kept under control via the pipeline controller
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and only this requires a dedicated reset if necessary.
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### Pipeline control
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You must connect the `O_Enable` port to the CE input of the corresponding pipeline registers.
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This is used to activate or deactivate the pipeline in full or via CE deactivated state.
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### AXI like Handshaking
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- **Input**: The `O_Ready` (active high) port is used to signal to the data-supplying component that data should be accepted.
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If it switches on `I_Valid` (active high), this in turn signals that data is ready to be accepted at its output.
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If both ports are active at the same time, the transfer is executed.
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- **Output**: The process runs analogously at the pipeline output.
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## History
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- 0.0.1 (2024-03-24) Initial version
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## Generics
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| Generic name | Type | Value | Description |
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| ---------------- | --------- | ----- | ----------------------------------------------------------------- |
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| G_PipelineStages | integer | 3 | Number of pipeline stages (FFs in the pipeline including I/O FFs) |
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| G_ResetActiveAt | std_logic | '1' | Reset active at this level |
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## Ports
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| Port name | Direction | Type | Description |
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| -------------------- | --------- | ----------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
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| I_CLK | in | std_logic | Clock signal; **Rising edge** triggered |
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| I_RST | in | std_logic | Reset signal; Active at `G_ResetActiveAt` |
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| I_CE | in | std_logic | Chip enable; Active high |
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| O_Enable | out | std_logic | Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br> **Note:** Connect `CE` of the registers to be controlled by this controller to `O_Enable`. |
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| Input-AXI-Handshake | in | Virtual bus | Input AXI like Handshake |
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| Output-AXI-Handshake | out | Virtual bus | Output AXI like Handshake |
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### Virtual Buses
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#### Input-AXI-Handshake
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| Port name | Direction | Type | Description |
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| --------- | --------- | --------- | ----------------------------------------------------------------------------------------- |
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| I_Valid | in | std_logic | Valid data flag; indicates that the data on `I_Data` of the connected registers is valid. |
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| O_Ready | out | std_logic | Ready flag; indicates that the connected registers is ready to accept data. |
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#### Output-AXI-Handshake
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| Port name | Direction | Type | Description |
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| --------- | --------- | --------- | ----------------------------------------------------------------------------------------- |
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| O_Valid | out | std_logic | Valid data flag; indicates that the data on `O_Data` of the connected registers is valid. |
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| I_Ready | in | std_logic | Ready flag; indicates that the external component is ready to accept data. |
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## Signals
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| Name | Type | Description |
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| ------- | ----------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------- |
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| R_Valid | std_logic_vector(G_PipelineStages - 1 downto 0) | Pipeline ready signal for each stage of the pipeline to indicate that the data in pipeline is valid |
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| C_Ready | std_logic | Ready signal for the pipeline controller to indicate that the pipeline can accept data; <br> mapped to `O_Enable` and `O_Ready` ports. |
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## Processes
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- P_ExternalFlags: ( R_Valid, C_Ready, I_CE )
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- **Description**
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Produce the `O_Valid`, `O_Enable`, and `O_Ready` signals for the pipeline controller. <br> - `O_Enable`, and `O_Ready` are **and** combined from the `C_Ready` and `I_CE` signals. <br> - `O_Valid` is the last bit of the `R_Valid` signal and represents the validity of the data in the last stage of the pipeline.
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- P_InternalFlags: ( R_Valid, I_Ready )
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- **Description**
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Produce the `C_Ready` signal for the pipeline controller, controlling the data flow in the pipeline. <br> `C_Ready` is asserted when the data is available in the last stage of the pipeline **and** the external component is ready to accept data **or** when no data is available in the last stage of the pipeline.
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- P_ValidPipeline: ( I_CLK )
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- **Description**
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Shift the pipeline stages with `R_Valid` signal as placeholder to control the validity of the data in the individual pipeline stages.
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---
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# Entity: PipelineRegister
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- **File**: PipelineRegister.vhd
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## Diagram
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## Description
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- Name: **Pipeline Register**
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- Version: 0.0.1
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- Author: _Maximilian Passarello ([Blog](mpassarello.de))_
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- License: [MIT](LICENSE)
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The pipeline register provides a simple way to pipeline combinatorial logic using the **register rebalancing** of the synthesis.
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### Core functions
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- **Register rebalancing**: The generic `G_RegisterBalancing` can be used
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to precisely configure how register rebalancing works.
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- **Number of registers**: The pipeline register instantiates a number of FFs corresponding
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to the generic `G_PipelineStages`.
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- **Data width**: The data width of the registers
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and the input/output vectors (std_logic_vector) is configured via the generic `G_Width`.
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### Register rebalancing
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The generic `G_RegisterBalancing` can be used to set the **Register Rebalancing** of the Xilinx ISE.
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The possible variants are
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- `no`: Deactivates the rebalancing register.
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- `yes`: Activates the rebalancing register in both directions (forwards and backwards).
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- `forward`: Activates the rebalancing register in the forward direction.
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This causes the synthesis to shift and reduce a **multiple** of FFs at the inputs of a LUT
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to a **single** FF forward at the output of a LUT.
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- `backward`: Activates the rebalancing register in the backward direction.
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This causes the synthesis to shift and duplicate a **single** FF at the output of a LUT
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backwards to a **multiple** of FFs at the input of a LUT.
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## History
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- 0.0.1 (2024-03-24) Initial version
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## Generics
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| Generic name | Type | Value | Description |
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| ------------------- | ------- | ----- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| G_PipelineStages | integer | 3 | Number of pipeline stages (Correspondent to the number of registers in the pipeline) |
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| G_Width | integer | 32 | Data width |
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| G_RegisterBalancing | string | "yes" | Register balancing attribute<br> - `no` : **Disable** register balancing, <br> - `yes`: **Enable** register balancing in both directions, <br> - `forward`: **Enable** register balancing and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br> - `backward`: **Enable** register balancing and moves a single FF at the output of a LUT to a set of FFs at its inputs. |
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## Ports
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| Port name | Direction | Type | Description |
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| --------- | --------- | -------------------------------------- | ----------------------------------------- |
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| I_CLK | in | std_logic | Clock signal; **Rising edge** triggered |
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| I_Enable | in | std_logic | Enable input from **Pipeline Controller** |
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| I_Data | in | std_logic_vector(G_Width - 1 downto 0) | Data input |
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| O_Data | out | std_logic_vector(G_Width - 1 downto 0) | Data output |
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## Signals
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| Name | Type | Description |
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| ------ | ------ | --------------------------------------------------------------------------- |
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| R_Data | T_Data | Pipeline register data signal; `G_PipelineStages` stages of `G_Width` bits. |
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## Types
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| Name | Type | Description |
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| ------ | ---- | --------------------------------------------------------------------------------------- |
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| T_Data | | Pipeline register data type; organized as an array (Stages) of std_logic_vector (Data). |
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## Processes
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- P_PipelineRegister: ( I_CLK )
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- **Description**
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Pipeline register and connection of the data from the input port to the first stage of the pipeline register. <br> **I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1)** -> O_Data
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- P_ForwardData: ( R_Data )
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- **Description**
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Connect (combinatoric) data from the last stage of the pipeline register to the output port. <br> I_Data -> R_Data(0) -> R_Data(1) -> ... -> **R_Data(G_PipelineStages - 1) -> O_Data**
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