Add first version.

.gitmodules

@@ -1,3 +1,3 @@
 [submodule "build"]
 	path = build
-	url = ssh://git@github.com:PxaMMaxP/Xilinx-ISE-Makefile.git
+	url = https://github.com/PxaMMaxP/Xilinx-ISE-Makefile.git

README.md

@@ -1,61 +1 @@
-# English
-
-## VHDL Project Template Using Xilinx Build Tools with Makefile
-
-Welcome to the VHDL Project Template repository. This project is designed to streamline your FPGA development process using the Xilinx ISE Build Tools, integrated with a convenient Makefile approach for building and synthesizing your VHDL designs.
-
-### Using the Makefile
-
-To use the Makefile for building your VHDL projects, ensure you have the Xilinx Build Tools installed on your system. The Makefile is specifically configured to work with these tools to automate the build process.
-
-For detailed instructions on how to use the Makefile, please refer to the following URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). This page contains comprehensive guidance on setup and usage to get you started quickly.
-
-### Directory Structure
-
-The project is organized into various subdirectories, each serving a specific role in the development process.
-
-#### `lib` Directory
-
-This directory is intended for individual modules of the project. Each module should be placed in its own subdirectory within the `lib` directory. This structure helps to keep the project organized and makes it easier to locate specific modules.
-
-#### `code` Directory
-
-This directory is intended for project-specific VHDL codes. Modules, on the other hand, should be placed in the subdirectory `../lib`.
-
-### Getting Started
-
-To begin using this VHDL Project Template, clone the repository to your local machine and follow the instructions provided in the subdirectory `README.md` files to understand the project layout. Then, head over to the URL mentioned above for details on using the Makefile with the Xilinx Build Tools.
-
-Thank you for choosing this VHDL Project Template. We hope it accelerates your development process and helps you achieve your project goals efficiently.
-
----
-
-# Deutsch
-
-## VHDL-Projektvorlage unter Verwendung von Xilinx Build Tools mit Makefile
-
-Willkommen im Repository der VHDL-Projektvorlage. Dieses Projekt wurde entwickelt, um Ihren FPGA-Entwicklungsprozess mit den Xilinx ISE Build Tools zu vereinfachen, integriert mit einem praktischen Makefile-Ansatz zum Bauen und Synthetisieren Ihrer VHDL-Designs.
-
-### Verwendung des Makefiles
-
-Um das Makefile für den Bau Ihrer VHDL-Projekte zu verwenden, stellen Sie sicher, dass die Xilinx Build Tools auf Ihrem System installiert sind. Das Makefile ist speziell so konfiguriert, dass es mit diesen Tools arbeitet, um den Bauprozess zu automatisieren.
-
-Für detaillierte Anweisungen zur Verwendung des Makefiles besuchen Sie bitte die folgende URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). Diese Seite enthält umfassende Anleitungen zur Einrichtung und Verwendung, damit Sie schnell starten können.
-
-### Verzeichnisstruktur
-
-Das Projekt ist in verschiedene Unterverzeichnisse organisiert, von denen jedes eine spezifische Rolle im Entwicklungsprozess spielt.
-
-#### `lib` Verzeichnis
-
-Dieses Verzeichnis ist für einzelne Module des Projekts vorgesehen. Jedes Modul sollte in seinem eigenen Unterordner innerhalb des `lib` Verzeichnisses platziert werden. Diese Struktur hilft, das Projekt organisiert zu halten und erleichtert das Auffinden spezifischer Module.
-
-#### `code` Verzeichnis
-
-Dieses Verzeichnis ist für projektspezifische VHDL-Codes vorgesehen. Module sollten hingegen im Unterordner `../lib` abgelegt werden.
-
-### Erste Schritte
-
-Um mit dieser VHDL-Projektvorlage zu beginnen, klonen Sie das Repository auf Ihre lokale Maschine und folgen Sie den Anweisungen in den `README.md`-Dateien der Unterverzeichnisse, um das Layout des Projekts zu verstehen. Anschließend besuchen Sie die oben genannte URL für Details zur Verwendung des Makefiles mit den Xilinx Build Tools.
-
-Vielen Dank, dass Sie sich für diese VHDL-Projektvorlage entschieden haben. Wir hoffen, dass sie Ihren Entwicklungsprozess beschleunigt und Ihnen hilft, Ihre Projektziele effizient zu erreichen.
+See at docs subdirectory for the documentation..

docs/PipelineController.md

@@ -0,0 +1,53 @@
+
+# Entity: PipelineController 
+- **File**: PipelineController.vhd
+
+## Diagram
+![Diagram](PipelineController.svg "Diagram")
+## Generics
+
+| Generic name     | Type      | Value | Description               |
+| ---------------- | --------- | ----- | ------------------------- |
+| G_PipelineStages | integer   | 3     | Number of pipeline stages |
+| G_ResetActiveAt  | std_logic | '1'   | Reset active at:          |
+
+## Ports
+
+| Port name            | Direction | Type        | Description                                                                                                                                                                |
+| -------------------- | --------- | ----------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
+| I_CLK                | in        | std_logic   | Clock signal; **Rising edge** triggered                                                                                                                                    |
+| I_RST                | in        | std_logic   | Reset signal; Active at `G_ResetActiveAt`                                                                                                                                  |
+| I_CE                 | in        | std_logic   | Chip enable; Active high                                                                                                                                                   |
+| O_Enable             | out       | std_logic   | Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br>  **Note:** Connect to `I_Enable` of the registers to be controlled by this controller. |
+| Input-AXI-Handshake  | in        | Virtual bus | Input AXI like Handshake                                                                                                                                                   |
+| Output-AXI-Handshake | out       | Virtual bus | Output AXI like Handshake                                                                                                                                                  |
+
+### Virtual Buses
+
+#### Input-AXI-Handshake
+
+| Port name | Direction | Type      | Description                                                                               |
+| --------- | --------- | --------- | ----------------------------------------------------------------------------------------- |
+| I_Valid   | in        | std_logic | Valid data flag; indicates that the data on `I_Data` of the connected registers is valid. |
+| O_Ready   | out       | std_logic | Ready flag; indicates that the connected registers is ready to accept data.               |
+#### Output-AXI-Handshake
+
+| Port name | Direction | Type      | Description                                                                               |
+| --------- | --------- | --------- | ----------------------------------------------------------------------------------------- |
+| O_Valid   | out       | std_logic | Valid data flag; indicates that the data on `O_Data` of the connected registers is valid. |
+| I_Ready   | in        | std_logic | Ready flag; indicates that the external component is ready to accept data.                |
+
+## Signals
+
+| Name    | Type                                            | Description                                                                                                                             |
+| ------- | ----------------------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------- |
+| R_Valid | std_logic_vector(G_PipelineStages - 1 downto 0) | Pipeline ready signal for each stage of the pipeline to indicate that the data in pipeline is valid                                     |
+| C_Ready | std_logic                                       | Ready signal for the pipeline controller to indicate that the pipeline can accept data; <br>  mapped to `O_Enable` and `O_Ready` ports. |
+
+## Processes
+- P_Flags: ( R_Valid, I_Ready )
+  - **Description**
+  Produce the `C_Ready` signal for the pipeline controller, controlling the data flow in the pipeline.
+- P_ValidPipeline: ( I_CLK )
+  - **Description**
+  Shift the pipeline stages with `R_Valid` signal as placeholder to control the pipeline stages.

docs/PipelineRegister.md

@@ -0,0 +1,39 @@
+
+# Entity: PipelineRegister 
+- **File**: PipelineRegister.vhd
+
+## Diagram
+![Diagram](PipelineRegister.svg "Diagram")
+## Generics
+
+| Generic name        | Type    | Value | Description                                                                                                                                                                                                                                                                                                                                                      |
+| ------------------- | ------- | ----- | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
+| G_PipelineStages    | integer | 3     | Number of pipeline stages                                                                                                                                                                                                                                                                                                                                        |
+| G_Width             | integer | 32    | Data width                                                                                                                                                                                                                                                                                                                                                       |
+| G_RegisterBalancing | string  | "yes" | Register balancing attribute<br>  - "no" : **Disable** register balancing, <br>  - "yes": **Enable** register balancing in both directions, <br>  - "forward": **Enable** and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br>  - "backward": **Enable** and moves a single FF at the output of a LUT to a set of FFs at its inputs. |
+
+## Ports
+
+| Port name | Direction | Type                                   | Description                               |
+| --------- | --------- | -------------------------------------- | ----------------------------------------- |
+| I_CLK     | in        | std_logic                              | Clock signal; **Rising edge** triggered   |
+| I_Enable  | in        | std_logic                              | Enable input from **Pipeline Controller** |
+| I_Data    | in        | std_logic_vector(G_Width - 1 downto 0) | Data input                                |
+| O_Data    | out       | std_logic_vector(G_Width - 1 downto 0) | Data output                               |
+
+## Signals
+
+| Name   | Type   | Description                                                                 |
+| ------ | ------ | --------------------------------------------------------------------------- |
+| R_Data | T_Data | Pipeline register data signal; `G_PipelineStages` stages of `G_Width` bits. |
+
+## Types
+
+| Name   | Type | Description                                                                             |
+| ------ | ---- | --------------------------------------------------------------------------------------- |
+| T_Data |      | Pipeline register data type; organized as an array (Stages) of std_logic_vector (Data). |
+
+## Processes
+- P_PipelineRegister: ( I_CLK )
+  - **Description**
+  Pipeline register I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1) -> O_Data

project.cfg

@@ -2,20 +2,20 @@
 
 # Project name
 # @remark The name of the project is used as default name for the top module and the ucf file
-PROJECT = 
+PROJECT = Pipeline
 
 # Target device
 # @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
-TARGET_PART = 
+TARGET_PART = xc3s1200e-4-fg320
 
 # Path to the Xilinx ISE installation
 XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 
 # Optional the name of the top module (default is the project name)
-# TOPLEVEL = 
+TOPLEVEL = Pipeline_pb
 
 # Optional the name of the ucf file (default is the project name)
-# CONSTRAINTS = 
+CONSTRAINTS = src/Pipeline_pb.ucf
 
 ## ## ## ## ## ## ## ##
 # ---------------------
@@ -25,7 +25,11 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # @example `VSOURCE += src/main.v` (add a single Verilog file per line)
 # @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
 
+VHDSOURCE += src/Pipeline_pb.vhd
+VHDSOURCE += src/PipelineController.vhd
+VHDSOURCE += src/PipelineRegister.vhd
 
+VHDTEST += tests/Pipeline_tb.vhd
 
 ## ## ## ## ## ## ## ##
 # ---------------------
@@ -35,18 +39,18 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
 # COMMON_OPTS = 
 # Options for the XST synthesizer
-# XST_OPTS =
+XST_OPTS = -opt_mode speed -opt_level 2 
 
 # Options for the NGDBuild tool
 # NGDBUILD_OPTS =
 
 # Options for the MAP tool
 # @example -mt 2 (multi-threading with 2 threads)
-# MAP_OPTS = 
+MAP_OPTS = -cm speed -ol high -detail -timing
 
 # Options for the PAR tool
 # @example -mt 2 (multi-threading with 2 threads)
-# PAR_OPTS = 
+PAR_OPTS = -ol high
 
 # Options for the BitGen tool
 # @example -g Compress (compress bitstream)

src/PipelineController.vhd

@@ -0,0 +1,83 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity PipelineController is
+    generic (
+        --@ Number of pipeline stages
+        G_PipelineStages : integer := 3;
+        --@ Reset active at:
+        G_ResetActiveAt : std_logic := '1'
+    );
+    port (
+        --@ Clock signal; **Rising edge** triggered
+        I_CLK : in std_logic;
+        --@ Reset signal; Active at `G_ResetActiveAt`
+        I_RST : in std_logic;
+        --@ Chip enable; Active high
+        I_CE : in std_logic;
+        --@ Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br>
+        --@ **Note:** Connect to `I_Enable` of the registers to be controlled by this controller.
+        O_Enable : out std_logic;
+        --@ @virtualbus Input-AXI-Handshake @dir in Input AXI like Handshake
+        --@ Valid data flag; indicates that the data on `I_Data` of the connected registers is valid.
+        I_Valid : in std_logic;
+        --@ Ready flag; indicates that the connected registers is ready to accept data.
+        O_Ready : out std_logic;
+        --@ @end
+        --@ @virtualbus Output-AXI-Handshake @dir out Output AXI like Handshake
+        --@ Valid data flag; indicates that the data on `O_Data` of the connected registers is valid.
+        O_Valid : out std_logic;
+        --@ Ready flag; indicates that the external component is ready to accept data.
+        I_Ready : in std_logic
+        --@ @end
+    );
+end entity PipelineController;
+
+architecture RTL of PipelineController is
+    --@ Pipeline ready signal for each stage of the pipeline to indicate that the data in pipeline is valid
+    signal R_Valid : std_logic_vector(G_PipelineStages - 1 downto 0) := (others => '0');
+    --@ Ready signal for the pipeline controller to indicate that the pipeline can accept data; <br>
+    --@ mapped to `O_Enable` and `O_Ready` ports.
+    signal C_Ready : std_logic := '1';
+begin
+
+    O_Valid <= R_Valid(R_Valid'high);
+
+    O_Enable <= C_Ready and I_CE;
+    O_Ready  <= C_Ready and I_CE;
+
+    --@ Produce the `C_Ready` signal for the pipeline controller,
+    --@ controlling the data flow in the pipeline.
+    P_Flags : process (R_Valid, I_Ready)
+    begin
+        if R_Valid(R_Valid'high) = '1' then
+            -- Data is available in the last stage of the pipeline.
+            if I_Ready = '1' then
+                -- O_Data is accepted from the external component.
+                C_Ready <= '1';
+            else
+                -- O_Data is not accepted from the external component.
+                C_Ready <= '0';
+            end if;
+        else
+            -- No data available in the last stage of the pipeline.
+            C_Ready <= '1';
+        end if;
+    end process;
+
+    --@ Shift the pipeline stages with `R_Valid` signal as placeholder to control the pipeline stages.
+    P_ValidPipeline : process (I_CLK)
+    begin
+        if rising_edge(I_CLK) then
+            if I_RST = G_ResetActiveAt then
+                R_Valid <= (others => '0');
+            elsif I_CE = '1' then
+                if C_Ready = '1' then
+                    R_Valid <= R_Valid(R_Valid'high - 1 downto R_Valid'low) & I_Valid;
+                end if;
+            end if;
+        end if;
+    end process;
+end architecture RTL;

src/PipelineRegister.vhd

@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity PipelineRegister is
+    generic (
+        --@ Number of pipeline stages
+        G_PipelineStages : integer := 3;
+        --@ Data width
+        G_Width : integer := 32;
+        --@ Register balancing attribute<br>
+        --@ - "no" : **Disable** register balancing, <br>
+        --@ - "yes": **Enable** register balancing in both directions, <br>
+        --@ - "forward": **Enable** and moves a set of FFs at the inputs of a LUT to a single FF at its output, <br>
+        --@ - "backward": **Enable** and moves a single FF at the output of a LUT to a set of FFs at its inputs.
+        G_RegisterBalancing : string := "yes"
+    );
+    port (
+        --@ Clock signal; **Rising edge** triggered
+        I_CLK : in std_logic;
+        --@ Enable input from **Pipeline Controller**
+        I_Enable : in std_logic;
+        --@ Data input
+        I_Data : in std_logic_vector(G_Width - 1 downto 0);
+        --@ Data output
+        O_Data : out std_logic_vector(G_Width - 1 downto 0) := (others => '0')
+    );
+end entity PipelineRegister;
+
+architecture RTL of PipelineRegister is
+    attribute register_balancing : string;
+
+    --@ Pipeline register data type; organized as an array (Stages) of std_logic_vector (Data).
+    type T_Data is array(0 to G_PipelineStages - 1) of std_logic_vector(G_Width - 1 downto 0);
+    --@ Pipeline register data signal; `G_PipelineStages` stages of `G_Width` bits.
+    signal R_Data : T_Data := (others => (others => '0'));
+    --@ Pipeline register balancing attribute from generic
+    attribute register_balancing of R_Data : signal is G_RegisterBalancing;
+begin
+
+    --@ Pipeline register I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1) -> O_Data
+    P_PipelineRegister : process (I_CLK)
+    begin
+        if rising_edge(I_CLK) then
+            if I_Enable = '1' then
+                for i in 0 to G_PipelineStages - 1 loop
+                    if i = 0 then
+                        R_Data(i) <= I_Data;
+                    else
+                        R_Data(i) <= R_Data(i - 1);
+                    end if;
+                end loop;
+            end if;
+        end if;
+    end process;
+
+    O_Data <= R_Data(G_PipelineStages - 1);
+
+end architecture RTL;

src/Pipeline_pb.ucf

@@ -0,0 +1,3 @@
+NET I_CLK	                    LOC = B8; 
+NET I_CLK	                    TNM_NET = CLOCK;
+TIMESPEC TS_CLOCK = PERIOD CLOCK 240 MHz HIGH 50 %;

src/Pipeline_pb.vhd

@@ -0,0 +1,118 @@
+--@ Performance Benchmarking Environment
+--@ This file is a wrapper for the module which is to be tested 
+--@ and capsulates the module with flip-flops to create a synchronous
+--@ interface for the module. This is necessary to test the synthesis
+--@ results of the module.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity Pipeline_pb is
+    generic (
+        --@ Number of pipeline stages
+        G_PipelineStages : integer := 3;
+        --@ Data width
+        G_Width : integer := 32;
+        --@ Register balancing attribute<br>
+        --@ - "no" : No register balancing <br>
+        --@ - "yes": Register balancing in both directions <br>
+        --@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
+        --@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
+        G_RegisterBalancing : string := "yes"
+    );
+    port (
+        I_CLK   : in std_logic;
+        I_RST   : in std_logic;
+        I_CE    : in std_logic;
+        I_Data  : in std_logic_vector(G_Width - 1 downto 0);
+        I_Valid : in std_logic;
+        O_Ready : out std_logic;
+        O_Data  : out std_logic_vector(G_Width - 1 downto 0);
+        O_Valid : out std_logic;
+        I_Ready : in std_logic
+    );
+end entity Pipeline_pb;
+
+architecture RTL of Pipeline_pb is
+    -- Keep attribute: Prevents the synthesis tool from removing the entity if is "true".
+    attribute keep : string;
+    -- IOB attribute: Attaches the FF to the IOB if is "true".
+    attribute IOB : string;
+
+    -- General Interace
+    signal R_RST : std_logic;
+    signal R_CE  : std_logic;
+    -- Attribute
+    attribute keep of R_RST, R_CE : signal is "true";
+    attribute IOB of R_RST, R_CE  : signal is "false";
+
+    -- Input Interface
+    signal R_DataIn   : std_logic_vector(G_Width - 1 downto 0);
+    signal R_ValidIn  : std_logic;
+    signal R_ReadyOut : std_logic;
+    -- Attribute
+    attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
+    attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut  : signal is "false";
+
+    -- Output Interface
+    signal R_DataOut  : std_logic_vector(G_Width - 1 downto 0);
+    signal R_ValidOut : std_logic;
+    signal R_ReadyIn  : std_logic;
+    -- Attribute
+    attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
+    attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn  : signal is "false";
+
+    signal C_PipelineEnable : std_logic;
+begin
+
+    BenchmarkEnvironmentFFs : process (I_CLK)
+    begin
+        if rising_edge(I_CLK) then
+            -- General Interace
+            R_RST <= I_RST;
+            R_CE  <= I_CE;
+
+            -- Input Interface
+            R_DataIn  <= I_Data;
+            R_ValidIn <= I_Valid;
+            O_Ready   <= R_ReadyOut;
+
+            -- Output Interface
+            O_Data    <= R_DataOut;
+            O_Valid   <= R_ValidOut;
+            R_ReadyIn <= I_Ready;
+        end if;
+    end process;
+
+    PipelineController : entity work.PipelineController
+        generic map(
+            G_PipelineStages => G_PipelineStages,
+            G_ResetActiveAt  => '1'
+        )
+        port map(
+            I_CLK    => I_CLK,
+            I_RST    => R_RST,
+            I_CE     => R_CE,
+            O_Enable => C_PipelineEnable,
+            I_Valid  => R_ValidIn,
+            O_Ready  => R_ReadyOut,
+            O_Valid  => R_ValidOut,
+            I_Ready  => R_ReadyIn
+        );
+
+    PipelineRegister : entity work.PipelineRegister
+        generic map(
+            G_PipelineStages    => G_PipelineStages,
+            G_Width             => G_Width,
+            G_RegisterBalancing => G_RegisterBalancing
+        )
+        port map(
+            I_CLK    => I_CLK,
+            I_Enable => C_PipelineEnable,
+            I_Data   => R_DataIn,
+            O_Data   => R_DataOut
+        );
+
+end architecture RTL;

tests/Pipeline_tb.vhd

@@ -0,0 +1,132 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Pipeline_tb is
+    -- The testbench does not require any ports
+end entity Pipeline_tb;
+
+architecture behavior of Pipeline_tb is
+    -- Clock signal period
+    constant period : time := 20 ns;
+
+    -- Adjustable wait times
+    constant write_delay : natural := 0; -- Wait time between write operations in clock cycles
+    constant read_delay  : natural := 0; -- Wait time between read operations in clock cycles
+
+    -- Adjustable number of data values to be written
+    constant writes : natural := 100;
+
+    -- Setting constants for the FIFO to be tested
+    constant K_Width             : integer := 32;    -- Data width of the FIFO
+    constant K_PipelineStages    : integer := 3;     -- Number of pipeline stages
+    constant K_RegisterBalancing : string  := "yes"; -- Register balancing attribute
+
+    -- Testbench signals
+    signal CLK : std_logic := '0';
+    signal RST : std_logic := '1';
+
+    signal I_WriteCE : std_logic                              := '0';
+    signal I_Data    : std_logic_vector(K_Width - 1 downto 0) := (others => 'U');
+    signal I_Valid   : std_logic                              := '0';
+    signal O_Ready   : std_logic;
+
+    signal I_ReadCE : std_logic := '0';
+    signal O_Data   : std_logic_vector(K_Width - 1 downto 0);
+    signal O_Valid  : std_logic;
+    signal I_Ready  : std_logic := '0';
+
+    signal CE : std_logic := '1';
+
+    signal PipelineEnable : std_logic;
+begin
+    CE <= I_WriteCE or I_ReadCE;
+
+    uut0 : entity work.PipelineController
+        generic map(
+            G_PipelineStages => K_PipelineStages,
+            G_ResetActiveAt  => '1'
+        )
+        port map(
+            I_CLK    => CLK,
+            I_RST    => RST,
+            I_CE     => CE,
+            O_Enable => PipelineEnable,
+            I_Valid  => I_Valid,
+            O_Ready  => O_Ready,
+            O_Valid  => O_Valid,
+            I_Ready  => I_Ready
+        );
+
+    uut1 : entity work.PipelineRegister
+        generic map(
+            G_PipelineStages    => K_PipelineStages,
+            G_Width             => K_Width,
+            G_RegisterBalancing => K_RegisterBalancing
+        )
+        port map(
+            I_CLK    => CLK,
+            I_Enable => PipelineEnable,
+            I_Data   => I_Data,
+            O_Data   => O_Data
+        );
+
+    -- Clock process
+    clocking : process
+    begin
+        while true loop
+            CLK <= '0';
+            wait for period / 2;
+            CLK <= '1';
+            wait for period / 2;
+        end loop;
+    end process;
+
+    -- Write process adapted for the falling edge of the clock signal
+    write_process : process
+    begin
+        wait for 100 ns; -- Initial wait time for reset and FIFO initialization
+        RST <= '0';
+        wait for period; -- Wait an additional clock cycle after reset
+        I_WriteCE <= '1';
+        wait until falling_edge(CLK);
+        for i in 0 to writes loop -- Writing loop for data values
+            if O_Ready = '0' then
+                wait on O_Ready until O_Ready = '1';
+                wait until falling_edge(CLK);
+            end if;
+
+            I_Data  <= std_logic_vector(to_unsigned(i, K_Width)); -- Data to be written
+            I_Valid <= '1';
+            wait until falling_edge(CLK);
+            I_Valid <= '0'; -- Reset 'valid' after writing
+            for j in 1 to write_delay loop
+                wait until falling_edge(CLK); -- Wait based on the set wait time
+            end loop;
+        end loop;
+        I_WriteCE <= '0'; -- Deactivate write signal after writing
+        wait;
+    end process;
+
+    -- Read process adapted for the falling edge of the clock signal
+    read_process : process
+    begin
+        wait for 110 ns; -- Delay to start writing
+        I_ReadCE <= '1';
+        while true loop
+            if O_Valid = '1' and I_Ready = '0' then
+                I_Ready <= '1'; -- Signal readiness to read
+                wait until falling_edge(CLK);
+                if read_delay /= 0 then
+                    I_Ready <= '0'; -- Reset the signal after reading
+                end if;
+                for j in 1 to read_delay loop
+                    wait until falling_edge(CLK); -- Wait based on the set wait time
+                end loop;
+            else
+                wait until falling_edge(CLK); -- Synchronize with the clock when not ready to read
+            end if;
+        end loop;
+    end process;
+
+end architecture behavior;

tests/Pipeline_tb.wcfg

@@ -0,0 +1,134 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="pipeline_tb" />
+            <top_module name="std_logic_1164" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="11" />
+   <wvobject fp_name="/pipeline_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/rst" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst</obj_property>
+      <obj_property name="ObjectShortName">rst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/i_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">i_data[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/i_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_valid</obj_property>
+      <obj_property name="ObjectShortName">i_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/o_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ready</obj_property>
+      <obj_property name="ObjectShortName">o_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/o_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">o_data[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/o_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_valid</obj_property>
+      <obj_property name="ObjectShortName">o_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/pipeline_tb/i_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_ready</obj_property>
+      <obj_property name="ObjectShortName">i_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider56" type="divider">
+      <obj_property name="label">Pipeline</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+   </wvobject>
+   <wvobject fp_name="group61" type="group">
+      <obj_property name="label">Controller</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/pipeline_tb/uut0/o_enable" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_enable</obj_property>
+         <obj_property name="ObjectShortName">o_enable</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut0/i_valid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_valid</obj_property>
+         <obj_property name="ObjectShortName">i_valid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut0/o_ready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_ready</obj_property>
+         <obj_property name="ObjectShortName">o_ready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut0/r_valid" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">r_valid[2:0]</obj_property>
+         <obj_property name="ObjectShortName">r_valid[2:0]</obj_property>
+         <obj_property name="Radix">BINARYRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut0/o_valid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_valid</obj_property>
+         <obj_property name="ObjectShortName">o_valid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut0/i_ready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_ready</obj_property>
+         <obj_property name="ObjectShortName">i_ready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider39" type="divider">
+         <obj_property name="label">Combinatoric</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut0/c_ready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">c_ready</obj_property>
+         <obj_property name="ObjectShortName">c_ready</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group67" type="group">
+      <obj_property name="label">Register</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/pipeline_tb/uut1/i_enable" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_enable</obj_property>
+         <obj_property name="ObjectShortName">i_enable</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut1/i_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_data[31:0]</obj_property>
+         <obj_property name="ObjectShortName">i_data[31:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut1/r_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">r_data[0:2]</obj_property>
+         <obj_property name="ObjectShortName">r_data[0:2]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         <wvobject fp_name="/pipeline_tb/uut1/r_data[0]" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">[0]</obj_property>
+            <obj_property name="ObjectShortName">r_data[0]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/pipeline_tb/uut1/r_data[1]" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">[1]</obj_property>
+            <obj_property name="ObjectShortName">r_data[1]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+         <wvobject fp_name="/pipeline_tb/uut1/r_data[2]" type="array" db_ref_id="1">
+            <obj_property name="ElementShortName">[2]</obj_property>
+            <obj_property name="ObjectShortName">r_data[2]</obj_property>
+            <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+         </wvobject>
+      </wvobject>
+      <wvobject fp_name="/pipeline_tb/uut1/o_data" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_data[31:0]</obj_property>
+         <obj_property name="ObjectShortName">o_data[31:0]</obj_property>
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>