Adds pipeline buffer and controller with testbench
Implements a pipeline buffer component supporting passthrough and register modes, controlled via a dedicated controller. Adds AXI-like handshake signals for data flow management. Includes a testbench to validate functionality with randomized delays. Addresses robust data buffering and flow control.
This commit is contained in:
52
src/PipelineBuffer.vhd
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52
src/PipelineBuffer.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity PipelineBuffer is
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generic (
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--@ Data width
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G_Width : integer := 32
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);
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port (
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--@ Clock signal; (**Rising edge** triggered)
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I_CLK : in std_logic := '0';
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--@ Enable input from **Pipeline Buffer Controller**
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--@ [1]: If low, data is passed through, else data is registered
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--@ [0]: Enable for register
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I_Enable : in std_logic_vector(1 downto 0) := (others => '0');
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--@ Data input
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I_Data : in std_logic_vector(G_Width - 1 downto 0) := (others => '0');
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--@ Data output
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O_Data : out std_logic_vector(G_Width - 1 downto 0) := (others => '0')
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);
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end entity PipelineBuffer;
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architecture RTL of PipelineBuffer is
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signal C_MUX : std_logic := '0';
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signal C_Enable : std_logic := '0';
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signal R_Data : std_logic_vector(G_Width - 1 downto 0) := (others => '0');
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begin
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C_MUX <= I_Enable(1);
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C_Enable <= I_Enable(0);
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P_MUX : process (C_MUX, I_Data, R_Data)
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begin
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if C_MUX = '0' then -- Passthrough mode
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O_Data <= I_Data;
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else -- Register mode
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O_Data <= R_Data;
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end if;
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end process;
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P_Register : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if C_Enable = '1' then
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R_Data <= I_Data;
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end if;
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end if;
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end process;
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end architecture;
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73
src/PipelineBufferController.vhd
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73
src/PipelineBufferController.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity PipelineBufferController is
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generic (
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--@ Reset active at this level
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G_ResetActiveAt : std_logic := '1'
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);
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port (
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--@ Clock signal; (**Rising edge** triggered)
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I_CLK : in std_logic := '0';
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--@ Reset; (**Synchronous**, **Active at `G_ResetActiveAt`**)
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I_RST : in std_logic := '0';
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--@ Chip enable; (**Synchronous**, **Active high**)
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I_CE : in std_logic := '1';
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--@ [1]: If low, data is passed through, else data is registered
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--@ [0]: Enable for register
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O_Enable : out std_logic_vector(1 downto 0) := (others => '0');
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--@ @virtualbus AXI-Flags-In @dir In Input interface for AXI-like handshake
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--@ AXI like valid; (**Synchronous**, **Active high**)
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I_Valid : in std_logic := '0';
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--@ AXI like ready; (**Synchronous**, **Active high**)
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O_Ready : out std_logic := '0';
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--@ @end
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--@ @virtualbus AXI-Flags-Out @dir Out Output interface for AXI-like handshake
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--@ AXI like valid; (**Synchronous**, **Active high**)
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O_Valid : out std_logic := '0';
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--@ AXI like ready; (**Synchronous**, **Active high**)
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I_Ready : in std_logic := '0'
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--@ @end
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);
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end entity PipelineBufferController;
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architecture RTL of PipelineBufferController is
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signal C_MUX : std_logic := '0';
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signal C_Enable : std_logic := '0';
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signal R_IsBuffered : std_logic := '0';
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begin
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--@ Set mux to buffered mode if data is available in the buffer.
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C_MUX <= R_IsBuffered;
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--@ Enable the buffer register if not buffered and chip enable is high.
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C_Enable <= I_CE and not R_IsBuffered;
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--@ Set the ready signal to high if not buffered.
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O_Ready <= not R_IsBuffered;
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--@ Set the valid signal to high if data is available in the buffer or if data is valid.
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O_Valid <= R_IsBuffered or I_Valid;
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process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_RST = G_ResetActiveAt then
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R_IsBuffered <= '0';
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elsif I_CE = '1' then
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if R_IsBuffered = '0' and I_Valid = '1' then
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R_IsBuffered <= '1';
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elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then
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R_IsBuffered <= '0';
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end if;
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end if;
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end if;
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end process;
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O_Enable(1) <= C_MUX;
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O_Enable(0) <= C_Enable;
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end architecture;
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169
tests/PipelineBuffer_tb.vhd
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169
tests/PipelineBuffer_tb.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.env.stop;
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entity PipelineBuffer_tb is
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end entity PipelineBuffer_tb;
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architecture RTL of PipelineBuffer_tb is
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-- Clock signal period
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constant K_Period : time := 20 ns;
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-- Zufallsverzögerungen
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constant K_WriteDelay : natural := 40;
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constant K_ReadDelay : natural := 60;
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-- Konstanten
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constant G_ResetActiveAt : std_logic := '1';
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constant G_Width : integer := 32;
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-- Zufalls-Seed
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shared variable seed1 : integer := 42;
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shared variable seed2 : integer := 1337;
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-- Randomfunktion
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impure function rand_int(min_val, max_val : integer) return integer is
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variable r : real;
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begin
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uniform(seed1, seed2, r);
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return integer(round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
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end function;
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-- Signale
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signal I_CLK : std_logic := '0';
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signal I_RST : std_logic := '1';
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signal I_CE : std_logic := '1';
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signal O_Enable : std_logic_vector(1 downto 0) := (others => '0');
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signal I_Valid : std_logic := '0';
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signal O_Ready : std_logic := '0';
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signal O_Valid : std_logic := '0';
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signal I_Ready : std_logic := '0';
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signal I_Data : std_logic_vector(G_Width - 1 downto 0) := (others => 'U');
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signal O_Data : std_logic_vector(G_Width - 1 downto 0) := (others => 'U');
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begin
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-- Clock
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Clocking : process
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begin
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while true loop
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I_CLK <= '0';
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wait for (K_Period / 2);
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I_CLK <= '1';
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wait for (K_Period / 2);
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end loop;
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end process;
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-- Reset
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I_RST <= G_ResetActiveAt, not G_ResetActiveAt after 100 ns;
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-- DUT: Controller
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i_PipelineBufferController : entity work.PipelineBufferController
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generic map(
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G_ResetActiveAt => G_ResetActiveAt
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)
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port map(
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I_CLK => I_CLK,
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I_RST => I_RST,
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I_CE => I_CE,
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O_Enable => O_Enable,
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I_Valid => I_Valid,
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O_Ready => O_Ready,
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O_Valid => O_Valid,
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I_Ready => I_Ready
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);
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-- DUT: Register
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i_PipelineBuffer : entity work.PipelineBuffer
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generic map(
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G_Width => G_Width
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_Enable,
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I_Data => I_Data,
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O_Data => O_Data
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);
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-- Write Stimulus
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Stim_Write : process
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variable delay : integer := 0;
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variable i : integer := 1;
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variable pending : boolean := false;
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begin
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I_Valid <= '0';
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I_Data <= (others => 'U');
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wait until I_RST = '0';
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while true loop
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wait until rising_edge(I_CLK);
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-- Neues Paket vorbereiten
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if not pending and delay = 0 then
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I_Data <= std_logic_vector(to_unsigned(i, G_Width));
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I_Valid <= '1';
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pending := true;
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report "Sende Paket #" & integer'image(i) severity note;
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end if;
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-- Handshake erfolgt
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if O_Ready = '1' and I_Valid = '1' then
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I_Valid <= '0';
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i := i + 1;
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delay := rand_int(1, K_WriteDelay);
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pending := false;
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end if;
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-- Verzögerung herunterzählen
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if delay > 0 and not pending then
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delay := delay - 1;
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end if;
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end loop;
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end process;
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-- Read Stimulus (robust)
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Stim_Read : process
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variable delay : integer := 0;
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variable expected : integer := 1;
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variable received : integer;
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variable consume_now : boolean := false;
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begin
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I_Ready <= '0';
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wait until I_RST = '0';
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while true loop
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wait until rising_edge(I_CLK);
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-- Wenn O_Valid vorhanden und kein Delay mehr: jetzt lesen
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if O_Valid = '1' and delay = 0 and not consume_now then
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I_Ready <= '1';
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consume_now := true; -- Warte auf nächste Gültigkeit
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end if;
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-- Sobald Handshake erfolgt (O_Valid & I_Ready), auswerten
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if O_Valid = '1' and I_Ready = '1' and consume_now then
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received := to_integer(unsigned(O_Data));
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if received = expected then
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report "Empfange Paket #" & integer'image(expected) severity note;
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else
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report "FEHLER bei Paket #" & integer'image(expected) &
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": erwartet " & integer'image(expected) &
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", empfangen " & integer'image(received) severity error;
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end if;
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expected := expected + 1;
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delay := rand_int(1, K_ReadDelay);
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consume_now := false;
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I_Ready <= '0';
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end if;
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-- Wartezeit herunterzählen
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if delay > 0 and not consume_now then
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delay := delay - 1;
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end if;
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end loop;
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end process;
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end architecture RTL;
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