Updated the DEPP VHDL interface entity and architecture to version 0.3.0, adding detailed annotations and a timing diagram for clarity. Standard library usage declarations have been optimized. Entity and architecture names, along with various signals, have been renamed to reflect the Digilent EPP interface standards. A description and history section has been included to improve documentation. Function `log2_ceil` is refined to `min_bits_for_states` for better semantic understanding. Port and signal names now adhere to the DEPP nomenclature for consistency with the Digilent Adept software. Additional comments have been added throughout to describe interface functions and signal usage more clearly.
Introduced a new UCF file specifying pin assignments, timing constraints, and net attributes for various components of the DEPP interface and system clock. This includes location constraints for the CLK signal, the eight Dout and Din signals, and DEPP control signals, with additional setup for a 50 MHz clock signal. Defines DEPP bus signal locations and applies CLOCK_DEDICATED_ROUTE settings to relevant nets, which ensures the FPGA's resources are mapped correctly, aligning with the required hardware configuration for optimal signal integrity and timing performance.
- Set the project name to DEPP for default module and UCF file naming.
- Define target device as 'xc3s1200e-4-fg320' for the build process.
- Specify the custom UCF file location under `code/DEPP.ucf`.
- Add VHD source file 'DEPP.vhd' to the compilation sources list.
- Select 'digilent' as the programmer tool and configure associated device and index settings for JTAG and flash.
