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Add UCF constraints for DEPP interface and clock

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Introduced a new UCF file specifying pin assignments, timing constraints, and net attributes for various components of the DEPP interface and system clock. This includes location constraints for the CLK signal, the eight Dout and Din signals, and DEPP control signals, with additional setup for a 50 MHz clock signal. Defines DEPP bus signal locations and applies CLOCK_DEDICATED_ROUTE settings to relevant nets, which ensures the FPGA's resources are mapped correctly, aligning with the required hardware configuration for optimal signal integrity and timing performance.
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0xMax42
2024-03-07 00:44:38 +01:00
parent 9146c18f43
commit 42e7c84fde
1 changed files with 36 additions and 0 deletions
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36
code/DEPP.ucf Normal file
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NET CLK LOC = B8;
NET CLK TNM_NET = CLOCK;
TIMESPEC TS_CLOCK = PERIOD CLOCK 50 MHz HIGH 50 %;
NET "Dout<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "Dout<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "Dout<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "Dout<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
NET "Dout<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
NET "Dout<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
NET "Dout<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
NET "Dout<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
NET "Din<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
NET "Din<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
NET "Din<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
NET "Din<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
NET "Din<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
NET "Din<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
NET "Din<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
NET "Din<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT,
NET "DEPP_AddressEnable" LOC = "V14" | CLOCK_DEDICATED_ROUTE = FALSE;
NET "DEPP_DataEnable" LOC = "U14" | CLOCK_DEDICATED_ROUTE = FALSE;
NET "DEPP_WriteEnable" LOC = "V16";
NET "DEPP_Wait" LOC = "N9";
NET "DEPP_Bus<0>" LOC = "R14";
NET "DEPP_Bus<1>" LOC = "R13";
NET "DEPP_Bus<2>" LOC = "P13";
NET "DEPP_Bus<3>" LOC = "T12";
NET "DEPP_Bus<4>" LOC = "N11";
NET "DEPP_Bus<5>" LOC = "R11";
NET "DEPP_Bus<6>" LOC = "P10";
NET "DEPP_Bus<7>" LOC = "R10";