Configure project settings for DEPP in project.cfg

- Set the project name to DEPP for default module and UCF file naming.
- Define target device as 'xc3s1200e-4-fg320' for the build process.
- Specify the custom UCF file location under `code/DEPP.ucf`.
- Add VHD source file 'DEPP.vhd' to the compilation sources list.
- Select 'digilent' as the programmer tool and configure associated device and index settings for JTAG and flash.

project.cfg

@@ -2,11 +2,11 @@
 
 # Project name
 # @remark The name of the project is used as default name for the top module and the ucf file
-PROJECT = 
+PROJECT = DEPP
 
 # Target device
 # @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
-TARGET_PART = 
+TARGET_PART = xc3s1200e-4-fg320
 
 # Path to the Xilinx ISE installation
 XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
@@ -15,7 +15,7 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # TOPLEVEL = 
 
 # Optional the name of the ucf file (default is the project name)
-# CONSTRAINTS = 
+CONSTRAINTS = code/DEPP.ucf
 
 ## ## ## ## ## ## ## ##
 # ---------------------
@@ -25,7 +25,7 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # @example `VSOURCE += src/main.v` (add a single Verilog file per line)
 # @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
 
-
+VHDSOURCE += code/DEPP.vhd
 
 ## ## ## ## ## ## ## ##
 # ---------------------
@@ -68,18 +68,18 @@ XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
 # The programmer to use
 # @example impact | digilent | xc3sprog
 # @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
-PROGRAMMER = 
+PROGRAMMER = digilent
 
 ## Digilent JTAG cable settings
 
 # @remark Use the `djtgcfg enum` command to list all available devices
-# DJTG_DEVICE = DOnbUsb
+DJTG_DEVICE = DOnbUsb
 
 # The index of the JTAG device for the `prog` target
-# DJTG_INDEX = 0
+DJTG_INDEX = 0
 
 # The index of the flash device for the `flash` target
-# DJTG_FLASH_INDEX = 1
+DJTG_FLASH_INDEX = 1
 
 ## ## ## ## ## ## ## ##
 # ---------------------