Initial commit
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build/
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209
Makefile
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Makefile
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###########################################################################
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## Xilinx ISE Makefile
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##
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## To the extent possible under law, the author(s) have dedicated all copyright
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## and related and neighboring rights to this software to the public domain
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## worldwide. This software is distributed without any warranty.
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###########################################################################
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include project.cfg
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###########################################################################
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# Default values
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###########################################################################
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ifndef XILINX
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$(error XILINX must be defined)
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endif
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ifndef PROJECT
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$(error PROJECT must be defined)
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endif
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ifndef TARGET_PART
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$(error TARGET_PART must be defined)
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endif
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TOPLEVEL ?= $(PROJECT)
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CONSTRAINTS ?= $(PROJECT).ucf
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BITFILE ?= build/$(PROJECT).bit
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COMMON_OPTS ?= -intstyle xflow
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XST_OPTS ?=
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NGDBUILD_OPTS ?=
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MAP_OPTS ?=
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?=
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FUSE_OPTS ?= -incremental
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PROGRAMMER ?= none
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IMPACT_OPTS ?= -batch impact.cmd
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DJTG_EXE ?= djtgcfg
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DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
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DJTG_INDEX ?= 0
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XC3SPROG_EXE ?= xc3sprog
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XC3SPROG_CABLE ?= none
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XC3SPROG_OPTS ?=
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###########################################################################
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# Internal variables, platform-specific definitions, and macros
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###########################################################################
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ifeq ($(OS),Windows_NT)
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XILINX := $(shell cygpath -m $(XILINX))
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CYG_XILINX := $(shell cygpath $(XILINX))
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EXE := .exe
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XILINX_PLATFORM ?= nt64
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PATH := $(PATH):$(CYG_XILINX)/bin/$(XILINX_PLATFORM)
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else
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EXE :=
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XILINX_PLATFORM ?= lin64
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PATH := $(PATH):$(XILINX)/bin/$(XILINX_PLATFORM)
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endif
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TEST_NAMES = $(foreach file,$(VTEST) $(VHDTEST),$(basename $(file)))
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TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
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RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
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cd build && $(XILINX)/bin/$(XILINX_PLATFORM)/$(1)
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# isim executables don't work without this
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export XILINX
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###########################################################################
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# Default build
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###########################################################################
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default: $(BITFILE)
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clean:
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rm -rf build
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build/$(PROJECT).prj: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@rm -f $@
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@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
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build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
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@cp build/$(PROJECT).prj $@
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@$(foreach file,$(VTEST),echo "verilog work \"../$(file)\"" >> $@;)
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@$(foreach file,$(VHDTEST),echo "vhdl work \"../$(file)\"" >> $@;)
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@echo "verilog work $(XILINX)/verilog/src/glbl.v" >> $@
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build/$(PROJECT).scr: project.cfg
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@echo "Updating $@"
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@mkdir -p build
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@rm -f $@
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@echo "run" \
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"-ifn $(PROJECT).prj" \
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"-ofn $(PROJECT).ngc" \
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"-ifmt mixed" \
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"$(XST_OPTS)" \
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"-top $(TOPLEVEL)" \
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"-ofmt NGC" \
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"-p $(TARGET_PART)" \
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> build/$(PROJECT).scr
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$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
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@mkdir -p build
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$(call RUN,xst) $(COMMON_OPTS) \
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-ifn $(PROJECT).scr
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$(call RUN,ngdbuild) $(COMMON_OPTS) $(NGDBUILD_OPTS) \
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-p $(TARGET_PART) -uc ../$(CONSTRAINTS) \
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$(PROJECT).ngc $(PROJECT).ngd
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$(call RUN,map) $(COMMON_OPTS) $(MAP_OPTS) \
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-p $(TARGET_PART) \
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-w $(PROJECT).ngd -o $(PROJECT).map.ncd $(PROJECT).pcf
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$(call RUN,par) $(COMMON_OPTS) $(PAR_OPTS) \
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-w $(PROJECT).map.ncd $(PROJECT).ncd $(PROJECT).pcf
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$(call RUN,bitgen) $(COMMON_OPTS) $(BITGEN_OPTS) \
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-w $(PROJECT).ncd $(PROJECT).bit
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@echo "\e[1;32m============ OK ============\e[m\n\n"
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@echo "\e[1;33m============ Reports.. ===========\e[m\n"
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@echo "\e[1;97m==== Synthesis Summary Report ====\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).srp\e[m\n"
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@echo "\e[1;97m======= Map Summary Report =======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).map.mrp\e[m\n"
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@echo "\e[1;97m======= PAR Summary Report =======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).par\e[m\n"
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@echo "\e[1;97m===== Pinout Summary Report ======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT)_pad.txt\e[m\n"
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###########################################################################
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# Testing (work in progress)
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###########################################################################
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trace: project.cfg $(BITFILE)
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$(call RUN,trce) $(COMMON_OPTS) $(TRACE_OPTS) \
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$(PROJECT).ncd $(PROJECT).pcf
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@echo "\n\e[1;33m============ Reports.. ===========\e[m\n"
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@echo "\e[1;97m===== Timing Summary Report ======\e[m"
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@echo "\e[1;35m ./build/$(PROJECT).twr\e[m\n"
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test: $(TEST_EXES)
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build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST)
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$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
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-prj $(PROJECT)_sim.prj \
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-o isim_$*$(EXE) \
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work.$* work.glbl
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isim: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
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isimgui: build/isim_$(TB)$(EXE)
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@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > build/isim_$(TB).cmd
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@echo "run all" >> build/isim_$(TB).cmd
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cd build ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
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###########################################################################
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# Programming
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###########################################################################
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ifeq ($(PROGRAMMER), impact)
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prog: $(BITFILE)
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sudo $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
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endif
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ifeq ($(PROGRAMMER), digilent)
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prog: $(BITFILE)
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yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), xc3sprog)
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prog: $(BITFILE)
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sudo $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
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endif
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ifeq ($(PROGRAMMER), none)
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prog:
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$(error PROGRAMMER must be set to use 'make prog')
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endif
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###########################################################################
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# Flash
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###########################################################################
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ifeq ($(PROGRAMMER), digilent)
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flash: $(BITFILE)
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yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
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endif
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###########################################################################
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# vim: set filetype=make: #
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45
README.md
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README.md
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# English
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## VHDL Project Template Using Xilinx Build Tools with Makefile
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Welcome to the VHDL Project Template repository. This project is designed to streamline your FPGA development process using the Xilinx ISE Build Tools, integrated with a convenient Makefile approach for building and synthesizing your VHDL designs.
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### Using the Makefile
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To use the Makefile for building your VHDL projects, ensure you have the Xilinx Build Tools installed on your system. The Makefile is specifically configured to work with these tools to automate the build process.
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For detailed instructions on how to use the Makefile, please refer to the following URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). This page contains comprehensive guidance on setup and usage to get you started quickly.
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### Directory Structure
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The project is organized into various subdirectories, each serving a specific role in the development process. For an explanation of the directory structure and the contents of each subdirectory, please refer to the `README.md` files located within the subdirectories. These documents provide valuable insights into how the project is organized and how to navigate the files and folders efficiently.
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### Getting Started
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To begin using this VHDL Project Template, clone the repository to your local machine and follow the instructions provided in the subdirectory `README.md` files to understand the project layout. Then, head over to the URL mentioned above for details on using the Makefile with the Xilinx Build Tools.
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Thank you for choosing this VHDL Project Template. We hope it accelerates your development process and helps you achieve your project goals efficiently.
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---
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# Deutsch
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## VHDL-Projektvorlage unter Verwendung von Xilinx Build Tools mit Makefile
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Willkommen im Repository der VHDL-Projektvorlage. Dieses Projekt wurde entwickelt, um Ihren FPGA-Entwicklungsprozess mit den Xilinx ISE Build Tools zu vereinfachen, integriert mit einem praktischen Makefile-Ansatz zum Bauen und Synthetisieren Ihrer VHDL-Designs.
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### Verwendung des Makefiles
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Um das Makefile für den Bau Ihrer VHDL-Projekte zu verwenden, stellen Sie sicher, dass die Xilinx Build Tools auf Ihrem System installiert sind. Das Makefile ist speziell so konfiguriert, dass es mit diesen Tools arbeitet, um den Bauprozess zu automatisieren.
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Für detaillierte Anweisungen zur Verwendung des Makefiles besuchen Sie bitte die folgende URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). Diese Seite enthält umfassende Anleitungen zur Einrichtung und Verwendung, damit Sie schnell starten können.
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### Verzeichnisstruktur
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Das Projekt ist in verschiedene Unterverzeichnisse organisiert, von denen jedes eine spezifische Rolle im Entwicklungsprozess spielt. Für eine Erklärung der Verzeichnisstruktur und des Inhalts jedes Unterverzeichnisses beachten Sie bitte die `README.md`-Dateien, die sich in den Unterverzeichnissen befinden. Diese Dokumente bieten wertvolle Einblicke, wie das Projekt organisiert ist und wie Sie effizient durch die Dateien und Ordner navigieren.
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### Erste Schritte
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Um mit dieser VHDL-Projektvorlage zu beginnen, klonen Sie das Repository auf Ihre lokale Maschine und folgen Sie den Anweisungen in den `README.md`-Dateien der Unterverzeichnisse, um das Layout des Projekts zu verstehen. Anschließend besuchen Sie die oben genannte URL für Details zur Verwendung des Makefiles mit den Xilinx Build Tools.
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Vielen Dank, dass Sie sich für diese VHDL-Projektvorlage entschieden haben. Wir hoffen, dass sie Ihren Entwicklungsprozess beschleunigt und Ihnen hilft, Ihre Projektziele effizient zu erreichen.
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13
code/README.md
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code/README.md
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# English
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# `code` Directory
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This directory is intended for project-specific VHDL codes. Modules, on the other hand, should be placed in the subdirectory `../lib`.
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---
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# Deutsch
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# `code` Verzeichnis
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Dieses Verzeichnis ist für projektspezifische VHDL-Codes vorgesehen. Module sollten hingegen im Unterordner `../lib` abgelegt werden.
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lib/README.md
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lib/README.md
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# English
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## `lib` Directory
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This directory is intended for individual modules of the project. Each module should be placed in its own subdirectory within the `lib` directory. This structure helps to keep the project organized and makes it easier to locate specific modules.
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---
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# Deutsch
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## `lib` Verzeichnis
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Dieses Verzeichnis ist für einzelne Module des Projekts vorgesehen. Jedes Modul sollte in seinem eigenen Unterordner innerhalb des `lib` Verzeichnisses platziert werden. Diese Struktur hilft, das Projekt organisiert zu halten und erleichtert das Auffinden spezifischer Module.
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85
project.cfg
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project.cfg
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## Main settings.. ##
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# Project name
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# @remark The name of the project is used as default name for the top module and the ucf file
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PROJECT =
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# Target device
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# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
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TARGET_PART =
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# Path to the Xilinx ISE installation
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XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
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# Optional the name of the top module (default is the project name)
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# TOPLEVEL =
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# Optional the name of the ucf file (default is the project name)
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# CONSTRAINTS =
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## ## ## ## ## ## ## ##
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# ---------------------
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## Source files settings.. ##
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# The source files to be compiled
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# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
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# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
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## ## ## ## ## ## ## ##
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# ---------------------
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## ISE executable settings.. ##
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# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
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# COMMON_OPTS =
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# Options for the XST synthesizer
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# XST_OPTS =
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# Options for the NGDBuild tool
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# NGDBUILD_OPTS =
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# Options for the MAP tool
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# @example -mt 2 (multi-threading with 2 threads)
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# MAP_OPTS =
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# Options for the PAR tool
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# @example -mt 2 (multi-threading with 2 threads)
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# PAR_OPTS =
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# Options for the BitGen tool
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# @example -g Compress (compress bitstream)
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# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
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# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
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# BITGEN_OPTS =
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# Options for the Trace tool
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# TRACE_OPTS =
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# Options for the Fuse tool
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# FUSE_OPTS =
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## ## ## ## ## ## ## ##
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# ---------------------
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## Programmer settings.. ##
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# The programmer to use
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# @example impact | digilent | xc3sprog
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# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
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PROGRAMMER =
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## Digilent JTAG cable settings
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# @remark Use the `djtgcfg enum` command to list all available devices
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# DJTG_DEVICE = DOnbUsb
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# The index of the JTAG device for the `prog` target
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# DJTG_INDEX = 0
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# The index of the flash device for the `flash` target
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# DJTG_FLASH_INDEX = 1
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## ## ## ## ## ## ## ##
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# ---------------------
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Reference in New Issue
Block a user