Refactor DEPP VHDL interface to 0.3.0
Updated the DEPP VHDL interface entity and architecture to version 0.3.0, adding detailed annotations and a timing diagram for clarity. Standard library usage declarations have been optimized. Entity and architecture names, along with various signals, have been renamed to reflect the Digilent EPP interface standards. A description and history section has been included to improve documentation. Function `log2_ceil` is refined to `min_bits_for_states` for better semantic understanding. Port and signal names now adhere to the DEPP nomenclature for consistency with the Digilent Adept software. Additional comments have been added throughout to describe interface functions and signal usage more clearly.
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227
code/DEPP.vhd
227
code/DEPP.vhd
@@ -1,110 +1,151 @@
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----------------------------------------------------------------------------------
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-- @Name EPP
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-- @Version 0.2
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-- @Author Maximilian Passarello
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-- @E-Mail atom-dragon@gmx.net
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-- @name Digilent EPP Interface
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-- @version 0.3.0
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-- @author Maximilian Passarello (mpassarello.de)
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--@ An EPP interface for Digilent FPGA boards
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--@ This interface is designed to be used with the Digilent EPP interface
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--@ and the Digilent Adept software.
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-- @history
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-- - 0.2.0 (2010.05.30) Initial version
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-- - 0.3.0 (2024.03.06) Refactored and commented
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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-- Timing Diagram's
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-- EPP Address Write
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--@ {
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--@ "signal": [
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--@ { "name": "DEPP_Bus", "wave": "xx3....xxx", "data": ["Adress"] },
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--@ { "name": "DEPP_WriteEnable", "wave": "1.0....1.." },
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--@ { "node": "...A...B", "phase": 0.15 },
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--@ { "name": "DEPP_AddressEnable", "wave": "1..0...1.." },
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--@ { "node": "...E.F.H.I", "phase": 0.15 },
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--@ { "node": ".C.D.G", "phase": 0.15 },
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--@ { "name": "DEPP_Wait", "wave": "x0...1...0" }
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--@ ],
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--@ "head": {
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--@ "text": "EPP Address Write"
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--@ },
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--@ "foot": {
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--@ "text": "EPP Address Write Cycle Timing Diagram"
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--@ },
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--@ "edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
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--@ }
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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ENTITY EPP IS
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GENERIC (RegisterQuant : INTEGER := 4);
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PORT (
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CLK : IN STD_LOGIC;
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CE : IN STD_LOGIC;
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RST : IN STD_LOGIC;
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EPPAddE : IN STD_LOGIC;
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EPPDataE : IN STD_LOGIC;
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EPPWE : IN STD_LOGIC;
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EPPD : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => 'Z');
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EPPWait : OUT STD_LOGIC;
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Dout : OUT STD_LOGIC_VECTOR((RegisterQuant * 8) - 1 DOWNTO 0);
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Din : IN STD_LOGIC_VECTOR((RegisterQuant * 8) - 1 DOWNTO 0));
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END EPP;
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entity DEPP is
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generic (
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--@ Number of 8-bit registers
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--@ `DOut` and `DIn` are 8 times this width
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RegisterQuant : integer := 1
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);
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port (
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--@ Clock signal
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--@ Rising edge triggered
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CLK : in std_logic;
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--@ Chip enable
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--@ `1` = enabled, `0` = disabled
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CE : in std_logic;
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--@ Reset signal
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--@ `1` = reset, `0` = normal operation
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RST : in std_logic;
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--@ @virtualbus EPP-Interface EPP Interface
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--@ Address strobe
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DEPP_AddressEnable : in std_logic;
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--@ Data strobe
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DEPP_DataEnable : in std_logic;
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--@ Transfer direction control
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--@ `1` = read (Host from DEPP), `0` = write (Host to DEPP)
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DEPP_WriteEnable : in std_logic;
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--@ Handshake signal
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--@ : `0` = ready for new cycle, `1` = closing current cycle; Keep the signal low to delay the cycle length
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DEPP_Wait : out std_logic;
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--@ Data/Adress bus
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DEPP_Bus : inout std_logic_vector(7 downto 0) := (others => 'Z');
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--@ @end
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--@ Data output
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DOut : out std_logic_vector((RegisterQuant * 8) - 1 downto 0);
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--@ Data input
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DIn : in std_logic_vector((RegisterQuant * 8) - 1 downto 0));
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end DEPP;
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ARCHITECTURE Behavioral OF EPP IS
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architecture Behavioral of DEPP is
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FUNCTION log2_ceil(N : INTEGER) RETURN INTEGER IS
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BEGIN
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IF (N <= 2) THEN
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RETURN 1;
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ELSE
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IF (N MOD 2 = 0) THEN
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RETURN 1 + log2_ceil(N/2);
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ELSE
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RETURN 1 + log2_ceil((N + 1)/2);
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END IF;
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END IF;
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END FUNCTION log2_ceil;
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--@ Function to calculate the number of bits needed to address the `N` registers
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function min_bits_for_states(N : integer) return integer is
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begin
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if (N <= 2) then
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return 1;
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else
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if (N mod 2 = 0) then
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return 1 + min_bits_for_states(N/2);
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else
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return 1 + min_bits_for_states((N + 1)/2);
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end if;
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end if;
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end function min_bits_for_states;
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TYPE RegisterType IS ARRAY(RegisterQuant - 1 DOWNTO 0)
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OF STD_LOGIC_VECTOR(7 DOWNTO 0);
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type RegisterType is array(RegisterQuant - 1 downto 0)
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of std_logic_vector(7 downto 0);
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SIGNAL RegistersIn : RegisterType;
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SIGNAL RegistersOut : RegisterType;
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signal RegistersIn : RegisterType;
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signal RegistersOut : RegisterType;
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SIGNAL EPPDInternal : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL Adress : STD_LOGIC_VECTOR(log2_ceil(RegisterQuant) - 1 DOWNTO 0);
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BEGIN
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signal EPPDInternal : std_logic_vector(7 downto 0);
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signal Adress : std_logic_vector(min_bits_for_states(RegisterQuant) - 1 downto 0);
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EPPWait <= '1' WHEN EPPDataE = '0' OR EPPAddE = '0' ELSE
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signal Intern_CE : std_logic := '1';
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signal Intern_RST : std_logic := '0';
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begin
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DEPP_Wait <= '1' when DEPP_DataEnable = '0' or DEPP_AddressEnable = '0' else
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'0';
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EPPD <= EPPDInternal WHEN (EPPWE = '1') ELSE
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DEPP_Bus <= EPPDInternal when (DEPP_WriteEnable = '1') else
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"ZZZZZZZZ";
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PROCESS (EPPAddE)
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BEGIN
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IF rising_edge(EPPAddE) THEN
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IF EPPWE = '0' THEN
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Adress <= EPPD(log2_ceil(RegisterQuant) - 1 DOWNTO 0);
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END IF;
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END IF;
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END PROCESS;
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DEPP_AddrIn : process (DEPP_AddressEnable)
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begin
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if rising_edge(DEPP_AddressEnable) then
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if DEPP_WriteEnable = '0' then
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Adress <= DEPP_Bus(min_bits_for_states(RegisterQuant) - 1 downto 0);
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end if;
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end if;
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end process;
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-- process(EPPAddE)
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-- begin
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-- if falling_edge(EPPAddE) then
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-- if EPPWE = '1' then
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-- EPPDInternal(log2_ceil(RegisterQuant)-1 downto 0) <= Adress;
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-- end if;
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-- end if;
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-- end process;
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PROCESS (EPPDataE)
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BEGIN
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IF rising_edge(EPPDataE) THEN
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IF EPPWE = '0' THEN
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RegistersOut(to_integer(unsigned(Adress))) <= EPPD;
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END IF;
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END IF;
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END PROCESS;
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DEPP_DIn : process (DEPP_DataEnable)
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begin
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if rising_edge(DEPP_DataEnable) then
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if DEPP_WriteEnable = '0' then
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RegistersOut(to_integer(unsigned(Adress))) <= DEPP_Bus;
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end if;
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end if;
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end process;
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EPPDInternal <= RegistersIn(to_integer(unsigned(Adress)));
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PROCESS (CLK)
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BEGIN
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IF rising_edge(CLK) THEN
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IF RST = '1' THEN
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Dout <= (OTHERS => '0');
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ELSIF CE = '1' THEN
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FOR i IN 0 TO RegisterQuant - 1 LOOP
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Dout(((i + 1) * 8) - 1 DOWNTO ((i) * 8)) <= RegistersOut(i);
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END LOOP;
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END IF;
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END IF;
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END PROCESS;
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DOutRegister : process (CLK)
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begin
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if rising_edge(CLK) then
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if Intern_RST = '1' then
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DOut <= (others => '0');
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elsif Intern_CE = '1' then
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for i in 0 to RegisterQuant - 1 loop
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DOut(((i + 1) * 8) - 1 downto ((i) * 8)) <= RegistersOut(i);
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end loop;
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end if;
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end if;
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end process;
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PROCESS (CLK)
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BEGIN
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IF rising_edge(CLK) THEN
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IF RST = '1' THEN
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NULL;
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ELSIF CE = '1' THEN
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FOR i IN 0 TO RegisterQuant - 1 LOOP
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RegistersIn(i) <= Din(((i + 1) * 8) - 1 DOWNTO ((i) * 8));
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END LOOP;
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END IF;
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END IF;
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END PROCESS;
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END Behavioral;
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DInRegister : process (CLK)
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begin
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if rising_edge(CLK) then
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if Intern_RST = '1' then
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null;
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elsif Intern_CE = '1' then
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for i in 0 to RegisterQuant - 1 loop
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RegistersIn(i) <= DIn(((i + 1) * 8) - 1 downto ((i) * 8));
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end loop;
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end if;
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end if;
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end process;
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end Behavioral;
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