Max P
319b51bf56
Replaces separate VGA Red, Green, and Blue output signals with a unified 8-bit VGA pixel bus for improved signal management. Updates signal mapping, testbench, and constraints file to reflect the new structure. Enhances maintainability and reduces signal complexity.
34 lines
848 B
VHDL
34 lines
848 B
VHDL
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
entity VGATimingGenerator_test_tb is
|
|
end;
|
|
|
|
architecture bench of VGATimingGenerator_test_tb is
|
|
-- Clock period
|
|
constant clk_period : time := 20 ns;
|
|
-- Generics
|
|
-- Ports
|
|
signal I_CLK : std_logic := '0';
|
|
signal O_HSync : std_logic;
|
|
signal O_VSync : std_logic;
|
|
signal O_Red : std_logic_vector(2 downto 0);
|
|
signal O_Green : std_logic_vector(2 downto 0);
|
|
signal O_Blue : std_logic_vector(1 downto 0);
|
|
begin
|
|
|
|
VGATimingGenerator_test_inst : entity work.VGATimingGenerator_test
|
|
port map (
|
|
I_CLK => I_CLK,
|
|
O_VGA_HSync => O_HSync,
|
|
O_VGA_VSync => O_VSync,
|
|
O_Red => O_Red,
|
|
O_Green => O_Green,
|
|
O_Blue => O_Blue
|
|
);
|
|
I_CLK <= not I_CLK after clk_period/2;
|
|
|
|
end;
|