library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity VGATimingGenerator_test_tb is
end;

architecture bench of VGATimingGenerator_test_tb is
  -- Clock period
  constant clk_period : time      := 20 ns;
  -- Generics
  -- Ports
  signal I_CLK        : std_logic := '0';
  signal O_HSync      : std_logic;
  signal O_VSync      : std_logic;
  signal O_Red        : std_logic_vector(2 downto 0);
  signal O_Green      : std_logic_vector(2 downto 0);
  signal O_Blue       : std_logic_vector(1 downto 0);
begin

  VGATimingGenerator_test_inst : entity work.VGATimingGenerator_test
    port map (
      I_CLK       => I_CLK,
      O_VGA_HSync => O_HSync,
      O_VGA_VSync => O_VSync,
      O_Red       => O_Red,
      O_Green     => O_Green,
      O_Blue      => O_Blue
      );
  I_CLK <= not I_CLK after clk_period/2;

end;