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319b51bf569f04b9227249e6f31b2665ee3cac15
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Max P 319b51bf56 Consolidates VGA output signals into a single pixel bus 
Replaces separate VGA Red, Green, and Blue output signals with a unified 8-bit VGA pixel bus for improved signal management.
Updates signal mapping, testbench, and constraints file to reflect the new structure.

Enhances maintainability and reduces signal complexity.
2025-04-25 16:07:57 +00:00
build @ 54949f43c0
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
src
Consolidates VGA output signals into a single pixel bus
2025-04-25 16:07:57 +00:00
tests
Consolidates VGA output signals into a single pixel bus
2025-04-25 16:07:57 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-03-27 15:59:31 +00:00
.gitmodules
Add submodule for Xilinx ISE Makefile
2025-03-27 15:59:05 +00:00
project.cfg
Adds VGA controller and testbench enhancements
2025-04-25 15:59:37 +00:00
Description
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60 KiB
Languages
VHDL 100%