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Add VGA Timing Generator implementation and testbench files

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Test @ 1080P
This commit is contained in:
0xMax42
2025-03-27 16:00:08 +00:00
parent 860108547f
commit c449016835
8 changed files with 544 additions and 0 deletions
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45
tests/VGATimingGenerator_tb.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VGATimingGenerator_tb is
end;
architecture bench of VGATimingGenerator_tb is
-- Clock period
constant clk_period : time := 40 ns;
-- Ports
signal I_CLK : std_logic := '0';
signal I_CE : std_logic := '1';
signal I_RST : std_logic := '1';
signal O_PixelReady : std_logic;
signal O_HSync : std_logic;
signal O_VSync : std_logic;
begin
VGATimingGenerator_inst : entity work.VGATimingGenerator
port map
(
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
O_PixelReady => O_PixelReady,
O_HSync => O_HSync,
O_VSync => O_VSync
);
I_CLK <= not I_CLK after clk_period/2;
process
begin
wait for 100 ms;
I_RST <= '0';
wait for 500 ms;
I_RST <= '1';
wait for 100 ms;
I_RST <= '0';
wait;
end process;
end;

33
tests/VGATimingGenerator_test_tb.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VGATimingGenerator_test_tb is
end;
architecture bench of VGATimingGenerator_test_tb is
-- Clock period
constant clk_period : time := 20 ns;
-- Generics
-- Ports
signal I_CLK : std_logic := '0';
signal O_HSync : std_logic;
signal O_VSync : std_logic;
signal O_Red : std_logic_vector(2 downto 0);
signal O_Green : std_logic_vector(2 downto 0);
signal O_Blue : std_logic_vector(1 downto 0);
begin
VGATimingGenerator_test_inst : entity work.VGATimingGenerator_test
port map (
I_CLK => I_CLK,
O_HSync => O_HSync,
O_VSync => O_VSync,
O_Red => O_Red,
O_Green => O_Green,
O_Blue => O_Blue
);
I_CLK <= not I_CLK after clk_period/2;
end;

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tests/default.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="math_real" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="vgatiminggenerator_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="6" />
<wvobject fp_name="/vgatiminggenerator_tb/VGATimingGenerator_inst/i_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_clk</obj_property>
<obj_property name="ObjectShortName">i_clk</obj_property>
</wvobject>
<wvobject fp_name="/vgatiminggenerator_tb/VGATimingGenerator_inst/i_ce" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_ce</obj_property>
<obj_property name="ObjectShortName">i_ce</obj_property>
</wvobject>
<wvobject fp_name="/vgatiminggenerator_tb/i_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_rst</obj_property>
<obj_property name="ObjectShortName">i_rst</obj_property>
</wvobject>
<wvobject fp_name="/vgatiminggenerator_tb/VGATimingGenerator_inst/o_pixelready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_pixelready</obj_property>
<obj_property name="ObjectShortName">o_pixelready</obj_property>
</wvobject>
<wvobject fp_name="/vgatiminggenerator_tb/VGATimingGenerator_inst/o_hsync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_hsync</obj_property>
<obj_property name="ObjectShortName">o_hsync</obj_property>
</wvobject>
<wvobject fp_name="/vgatiminggenerator_tb/VGATimingGenerator_inst/o_vsync" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_vsync</obj_property>
<obj_property name="ObjectShortName">o_vsync</obj_property>
</wvobject>
</wave_config>