33 lines
760 B
VHDL
33 lines
760 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity VGATimingGenerator_test_tb is
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end;
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architecture bench of VGATimingGenerator_test_tb is
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-- Clock period
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constant clk_period : time := 20 ns;
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-- Generics
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-- Ports
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signal I_CLK : std_logic := '0';
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signal O_HSync : std_logic;
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signal O_VSync : std_logic;
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signal O_Red : std_logic_vector(2 downto 0);
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signal O_Green : std_logic_vector(2 downto 0);
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signal O_Blue : std_logic_vector(1 downto 0);
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begin
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VGATimingGenerator_test_inst : entity work.VGATimingGenerator_test
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port map (
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I_CLK => I_CLK,
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O_HSync => O_HSync,
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O_VSync => O_VSync,
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O_Red => O_Red,
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O_Green => O_Green,
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O_Blue => O_Blue
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);
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I_CLK <= not I_CLK after clk_period/2;
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end; |