45 lines
1.0 KiB
VHDL
45 lines
1.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity VGATimingGenerator_tb is
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end;
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architecture bench of VGATimingGenerator_tb is
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-- Clock period
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constant clk_period : time := 40 ns;
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-- Ports
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signal I_CLK : std_logic := '0';
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signal I_CE : std_logic := '1';
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signal I_RST : std_logic := '1';
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signal O_PixelReady : std_logic;
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signal O_HSync : std_logic;
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signal O_VSync : std_logic;
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begin
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VGATimingGenerator_inst : entity work.VGATimingGenerator
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port map
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(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_PixelReady => O_PixelReady,
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O_HSync => O_HSync,
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O_VSync => O_VSync
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);
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I_CLK <= not I_CLK after clk_period/2;
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process
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begin
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wait for 100 ms;
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I_RST <= '0';
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wait for 500 ms;
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I_RST <= '1';
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wait for 100 ms;
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I_RST <= '0';
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wait;
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end process;
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end; |