library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity VGATimingGenerator_tb is
end;

architecture bench of VGATimingGenerator_tb is
    -- Clock period
    constant clk_period : time := 40 ns;
    -- Ports
    signal I_CLK        : std_logic := '0';
    signal I_CE         : std_logic := '1';
    signal I_RST        : std_logic := '1';
    signal O_PixelReady : std_logic;
    signal O_HSync      : std_logic;
    signal O_VSync      : std_logic;
begin

    VGATimingGenerator_inst : entity work.VGATimingGenerator
        port map
        (
            I_CLK        => I_CLK,
            I_CE         => I_CE,
            I_RST        => I_RST,
            O_PixelReady => O_PixelReady,
            O_HSync      => O_HSync,
            O_VSync      => O_VSync
        );

    I_CLK <= not I_CLK after clk_period/2;

    process
    begin
        wait for 100 ms;
        I_RST <= '0';
        wait for 500 ms;
        I_RST <= '1';
        wait for 100 ms;
        I_RST <= '0';
        wait;
    end process;

end;