Max P a143e8a1aa refactor: Simplifies ready signal logic in buffer controller ...

- Removes redundant signal and assigns directly to output.
- Simplifies the state update logic for the ready signal.

2025-07-11 10:52:06 +00:00

..

.gitkeep

Initial commit

2024-03-24 01:24:47 +01:00

Pipeline_pb_Module.vhd

feat: implements pipelined module chaining for performance

2025-07-11 10:05:02 +00:00

Pipeline_pb.ucf

refactor: adjusts pipeline parameters for performance

2025-07-11 10:15:49 +00:00

Pipeline_pb.vhd

refactor: adjusts pipeline parameters for performance

2025-07-11 10:15:49 +00:00

PipelineBuffer.vhd

Adds pipeline buffer and controller with testbench

2025-04-19 20:39:13 +00:00

PipelineBufferController.vhd

refactor: Simplifies ready signal logic in buffer controller

2025-07-11 10:52:06 +00:00

PipelineController.vhd

Refactors pipeline controllers and registers for flexibility

2025-04-16 17:24:51 +00:00

PipelineFilter.vhd

Adds configurable PipelineFilter with AXI-like handshake

2025-04-16 17:25:35 +00:00

PipelineRegister.vhd

Refactors pipeline controllers and registers for flexibility

2025-04-16 17:24:51 +00:00

PipelineStage.vhd

Adds configurable pipeline stage module

2025-04-16 17:25:17 +00:00

PipelineSwitch.vhd

Standardizes formatting and adds output signal

2025-04-24 18:29:53 +00:00