refactor: adjusts pipeline parameters for performance

- Changes clock frequency to 280 MHz.
- Reduces pipeline module count to improve performance.

src/Pipeline_pb.ucf

@@ -1,4 +1,4 @@
 #NET I_CLK	                    LOC = AG18; 
 NET I_CLK	                    LOC = B8; 
 NET I_CLK	                    TNM_NET = CLOCK;
-TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %;
+TIMESPEC TS_CLOCK = PERIOD CLOCK 280 MHz HIGH 50 %;

src/Pipeline_pb.vhd

@@ -26,7 +26,7 @@ entity Pipeline_pb is
         --@ - false : Direct connection (bypass)
         G_EnablePipelineBuffer : boolean := true;
         --@ How many Pipeline modules shall be chained?
-        G_PipelineModules      : integer := 250;
+        G_PipelineModules      : integer := 20;
         --@ Enable chip enable signal
         G_Enable_CE            : boolean := false;
         --@ Enable reset signal