From 5e1a3c2161bcdd7b082c202ee4b404b7b7d2a7bf Mon Sep 17 00:00:00 2001 From: Max P Date: Fri, 11 Jul 2025 10:15:49 +0000 Subject: [PATCH] refactor: adjusts pipeline parameters for performance - Changes clock frequency to 280 MHz. - Reduces pipeline module count to improve performance. --- src/Pipeline_pb.ucf | 2 +- src/Pipeline_pb.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Pipeline_pb.ucf b/src/Pipeline_pb.ucf index 9395e8c..a414f3c 100644 --- a/src/Pipeline_pb.ucf +++ b/src/Pipeline_pb.ucf @@ -1,4 +1,4 @@ #NET I_CLK LOC = AG18; NET I_CLK LOC = B8; NET I_CLK TNM_NET = CLOCK; -TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %; \ No newline at end of file +TIMESPEC TS_CLOCK = PERIOD CLOCK 280 MHz HIGH 50 %; \ No newline at end of file diff --git a/src/Pipeline_pb.vhd b/src/Pipeline_pb.vhd index 8cd37f6..3e54ad2 100644 --- a/src/Pipeline_pb.vhd +++ b/src/Pipeline_pb.vhd @@ -26,7 +26,7 @@ entity Pipeline_pb is --@ - false : Direct connection (bypass) G_EnablePipelineBuffer : boolean := true; --@ How many Pipeline modules shall be chained? - G_PipelineModules : integer := 250; + G_PipelineModules : integer := 20; --@ Enable chip enable signal G_Enable_CE : boolean := false; --@ Enable reset signal