Introduces the PipelineSwitch component with configurable routing behavior based on input comparison modes. Implements modes such as "none", "or", "and", "xor", "equal", and others. Adds a comprehensive testbench to validate functionality across all supported modes.
Implements a pipeline buffer component supporting passthrough and register modes, controlled via a dedicated controller.
Adds AXI-like handshake signals for data flow management.
Includes a testbench to validate functionality with randomized delays.
Addresses robust data buffering and flow control.
Introduces a comprehensive VHDL testbench for the PipelineFilter entity, covering various mask modes ("none", "or", "and", "xor", "equal", "not_equal").
Includes signal setup, instance mapping, and test cases to validate filtering behavior for each mode.
Ensures correct functionality and highlights potential errors during simulation.
Updates random seed values and adjusts pipeline configuration constants for improved testing flexibility. Refactors write and read processes for clarity, adding additional checks and error handling. Introduces `stop` function to terminate simulation on critical errors.
Enhances test coverage and simulation reliability.
Enhanced the PipelineController's validity logic to handle single-stage configurations properly. This update ensures that the validity bit is correctly updated for systems that operate with only one pipeline stage, addressing a potential logic flaw in previous versions. Additionally, clarified documentation for random number generation in pipeline testbench.
- Introduce comprehensive documentation for Pipeline Controller and Register, detailing core functions, generics, ports, and processes. Focus on data flow control, validity control, adjustability, and register rebalancing mechanisms.
- Implement AXI-Like handshaking in Pipeline Controller for improved input and output data handling, supporting active-high ready and valid signals for efficient data transfer.
- Refine Pipeline Register with register rebalancing options (no, yes, forward, backward) to optimize combinatorial logic pipelining in synthesis, configurable via `G_RegisterBalancing` generic.
- Update generics and ports descriptions to reflect the inclusion of I/O FFs in pipeline depth calculation and clarify the reset active level and handshaking protocol.
- Extend VHDL source for both modules to embody described functionalities and adjustments, ensuring alignment with documentation enhancements.
- Augment testbench `Pipeline_tb.vhd` with random intervals for write and read operations, emphasizing dynamic testing scenarios.
