HDL/Pipeline-AXI-Handshake
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Enhance Pipeline Controller and Register with AXI-Like Handshaking and Register Rebalancing

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- Introduce comprehensive documentation for Pipeline Controller and Register, detailing core functions, generics, ports, and processes. Focus on data flow control, validity control, adjustability, and register rebalancing mechanisms.
- Implement AXI-Like handshaking in Pipeline Controller for improved input and output data handling, supporting active-high ready and valid signals for efficient data transfer.
- Refine Pipeline Register with register rebalancing options (no, yes, forward, backward) to optimize combinatorial logic pipelining in synthesis, configurable via `G_RegisterBalancing` generic.
- Update generics and ports descriptions to reflect the inclusion of I/O FFs in pipeline depth calculation and clarify the reset active level and handshaking protocol.
- Extend VHDL source for both modules to embody described functionalities and adjustments, ensuring alignment with documentation enhancements.
- Augment testbench `Pipeline_tb.vhd` with random intervals for write and read operations, emphasizing dynamic testing scenarios.
This commit is contained in:
0xMax42
2024-03-24 19:47:01 +01:00
parent e03dc4e0c8
commit abb4a9f10a
6 changed files with 350 additions and 101 deletions
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140
tests/Pipeline_tb.vhd
View File

@@ -1,21 +1,29 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Pipeline_tb is
-- The testbench does not require any ports
end entity Pipeline_tb;
architecture behavior of Pipeline_tb is
shared variable seed1 : integer := 483;
shared variable seed2 : integer := 847;
impure function rand_int(min_val, max_val : integer) return integer is
variable r : real;
begin
uniform(seed1, seed2, r);
return integer(
round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;
-- Clock signal period
constant period : time := 20 ns;
-- Adjustable wait times
constant write_delay : natural := 0; -- Wait time between write operations in clock cycles
constant read_delay : natural := 0; -- Wait time between read operations in clock cycles
-- Adjustable number of data values to be written
constant writes : natural := 100;
constant write_delay : natural := 10; -- Maximal wait time between write operations in clock cycles
constant read_delay : natural := 10; -- Maximal wait time between read operations in clock cycles
-- Setting constants for the FIFO to be tested
constant K_Width : integer := 32; -- Data width of the FIFO
@@ -25,22 +33,18 @@ architecture behavior of Pipeline_tb is
-- Testbench signals
signal CLK : std_logic := '0';
signal RST : std_logic := '1';
signal CE : std_logic := '1';
signal I_WriteCE : std_logic := '0';
signal I_Data : std_logic_vector(K_Width - 1 downto 0) := (others => 'U');
signal I_Valid : std_logic := '0';
signal O_Ready : std_logic;
signal I_Data : std_logic_vector(K_Width - 1 downto 0) := (others => 'U');
signal I_Valid : std_logic := '0';
signal O_Ready : std_logic;
signal I_ReadCE : std_logic := '0';
signal O_Data : std_logic_vector(K_Width - 1 downto 0);
signal O_Valid : std_logic;
signal I_Ready : std_logic := '0';
signal CE : std_logic := '1';
signal O_Data : std_logic_vector(K_Width - 1 downto 0) := (others => 'U');
signal O_Valid : std_logic;
signal I_Ready : std_logic := '0';
signal PipelineEnable : std_logic;
begin
CE <= I_WriteCE or I_ReadCE;
uut0 : entity work.PipelineController
generic map(
@@ -72,61 +76,79 @@ begin
);
-- Clock process
clocking : process
Clocking : process
begin
while true loop
CLK <= '0';
wait for period / 2;
wait for (period / 2);
CLK <= '1';
wait for period / 2;
wait for (period / 2);
end loop;
end process;
-- Write process adapted for the falling edge of the clock signal
write_process : process
begin
wait for 100 ns; -- Initial wait time for reset and FIFO initialization
RST <= '0';
wait for period; -- Wait an additional clock cycle after reset
I_WriteCE <= '1';
wait until falling_edge(CLK);
for i in 0 to writes loop -- Writing loop for data values
if O_Ready = '0' then
wait on O_Ready until O_Ready = '1';
wait until falling_edge(CLK);
end if;
-- Clock enable process
-- This process is used to enable the clock signal for a certain amount of time
-- and only for the Pipeline Controller to check if the dataflow is working correctly.
-- ClockEnable : process
-- begin
-- while true loop
-- CE <= '1';
-- wait for 1000 ns;
-- CE <= '0';
-- wait for 500 ns;
-- end loop;
-- end process;
I_Data <= std_logic_vector(to_unsigned(i, K_Width)); -- Data to be written
I_Valid <= '1';
wait until falling_edge(CLK);
I_Valid <= '0'; -- Reset 'valid' after writing
for j in 1 to write_delay loop
wait until falling_edge(CLK); -- Wait based on the set wait time
end loop;
end loop;
I_WriteCE <= '0'; -- Deactivate write signal after writing
wait;
end process;
-- 100 ns Reset
RST <= '1', '0' after 100 ns;
-- Read process adapted for the falling edge of the clock signal
read_process : process
-- Write process
Write : process (CLK)
variable delay : integer := 0;
variable i : integer := 1;
begin
wait for 110 ns; -- Delay to start writing
I_ReadCE <= '1';
while true loop
if O_Valid = '1' and I_Ready = '0' then
I_Ready <= '1'; -- Signal readiness to read
wait until falling_edge(CLK);
if read_delay /= 0 then
I_Ready <= '0'; -- Reset the signal after reading
end if;
for j in 1 to read_delay loop
wait until falling_edge(CLK); -- Wait based on the set wait time
end loop;
if rising_edge(CLK) then
if RST = '1' then
I_Valid <= '0';
delay := write_delay;
i := 1;
I_Data <= (others => 'U');
else
wait until falling_edge(CLK); -- Synchronize with the clock when not ready to read
if O_Ready = '1' and delay = 0 then
I_Data <= std_logic_vector(to_unsigned(i, K_Width)); -- Data to be written
I_Valid <= '1';
i := i + 1;
delay := rand_int(1, write_delay);
elsif O_Ready = '1' and I_Valid = '1' then
I_Valid <= '0';
end if;
if delay /= 0 then
delay := delay - 1;
end if;
end if;
end loop;
end if;
end process;
-- Read process
Read : process (CLK)
variable delay : integer := 0;
begin
if rising_edge(CLK) then
if RST = '1' then
I_Ready <= '0';
delay := read_delay;
else
if O_Valid = '1' and delay = 0 then
I_Ready <= '1'; -- Signal readiness to read
delay := rand_int(1, read_delay);
elsif O_Valid = '1' and I_Ready = '1' then
I_Ready <= '0';
end if;
if delay /= 0 then
delay := delay - 1;
end if;
end if;
end if;
end process;
end architecture behavior;

43
tests/Pipeline_tb.wcfg
View File

@@ -13,7 +13,7 @@
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="11" />
<WVObjectSize size="13" />
<wvobject fp_name="/pipeline_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
@@ -22,6 +22,10 @@
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/ce" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">ce</obj_property>
<obj_property name="ObjectShortName">ce</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/i_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">i_data[31:0]</obj_property>
<obj_property name="ObjectShortName">i_data[31:0]</obj_property>
@@ -47,6 +51,8 @@
<wvobject fp_name="/pipeline_tb/i_ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">i_ready</obj_property>
<obj_property name="ObjectShortName">i_ready</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00ff00</obj_property>
</wvobject>
<wvobject fp_name="divider56" type="divider">
<obj_property name="label">Pipeline</obj_property>
@@ -54,6 +60,10 @@
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/pipelineenable" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">pipelineenable</obj_property>
<obj_property name="ObjectShortName">pipelineenable</obj_property>
</wvobject>
<wvobject fp_name="group61" type="group">
<obj_property name="label">Controller</obj_property>
<obj_property name="DisplayName">label</obj_property>
@@ -69,10 +79,27 @@
<obj_property name="ElementShortName">o_ready</obj_property>
<obj_property name="ObjectShortName">o_ready</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut0/r_valid" type="array" db_ref_id="1">
<obj_property name="ElementShortName">r_valid[2:0]</obj_property>
<obj_property name="ObjectShortName">r_valid[2:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
<wvobject fp_name="vbus67" type="vbus" db_ref_id="1">
<obj_property name="label">r_valid[0:2]</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/pipeline_tb/uut0/r_valid[0]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">r_valid[0]</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut0/r_valid[1]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">r_valid[1]</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut0/r_valid[2]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">r_valid[2]</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut0/o_valid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">o_valid</obj_property>
@@ -113,16 +140,22 @@
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">r_data[0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut1/r_data[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">r_data[1]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut1/r_data[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">r_data[2]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff00ff</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/pipeline_tb/uut1/o_data" type="array" db_ref_id="1">