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132
tests/Pipeline_tb.vhd
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132
tests/Pipeline_tb.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Pipeline_tb is
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-- The testbench does not require any ports
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end entity Pipeline_tb;
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architecture behavior of Pipeline_tb is
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-- Clock signal period
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constant period : time := 20 ns;
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-- Adjustable wait times
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constant write_delay : natural := 0; -- Wait time between write operations in clock cycles
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constant read_delay : natural := 0; -- Wait time between read operations in clock cycles
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-- Adjustable number of data values to be written
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constant writes : natural := 100;
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-- Setting constants for the FIFO to be tested
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constant K_Width : integer := 32; -- Data width of the FIFO
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constant K_PipelineStages : integer := 3; -- Number of pipeline stages
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constant K_RegisterBalancing : string := "yes"; -- Register balancing attribute
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-- Testbench signals
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signal CLK : std_logic := '0';
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signal RST : std_logic := '1';
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signal I_WriteCE : std_logic := '0';
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signal I_Data : std_logic_vector(K_Width - 1 downto 0) := (others => 'U');
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signal I_Valid : std_logic := '0';
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signal O_Ready : std_logic;
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signal I_ReadCE : std_logic := '0';
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signal O_Data : std_logic_vector(K_Width - 1 downto 0);
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signal O_Valid : std_logic;
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signal I_Ready : std_logic := '0';
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signal CE : std_logic := '1';
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signal PipelineEnable : std_logic;
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begin
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CE <= I_WriteCE or I_ReadCE;
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uut0 : entity work.PipelineController
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generic map(
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G_PipelineStages => K_PipelineStages,
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => CLK,
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I_RST => RST,
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I_CE => CE,
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O_Enable => PipelineEnable,
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I_Valid => I_Valid,
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O_Ready => O_Ready,
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O_Valid => O_Valid,
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I_Ready => I_Ready
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);
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uut1 : entity work.PipelineRegister
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generic map(
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G_PipelineStages => K_PipelineStages,
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G_Width => K_Width,
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G_RegisterBalancing => K_RegisterBalancing
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)
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port map(
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I_CLK => CLK,
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I_Enable => PipelineEnable,
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I_Data => I_Data,
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O_Data => O_Data
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);
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-- Clock process
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clocking : process
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begin
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while true loop
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CLK <= '0';
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wait for period / 2;
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CLK <= '1';
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wait for period / 2;
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end loop;
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end process;
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-- Write process adapted for the falling edge of the clock signal
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write_process : process
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begin
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wait for 100 ns; -- Initial wait time for reset and FIFO initialization
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RST <= '0';
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wait for period; -- Wait an additional clock cycle after reset
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I_WriteCE <= '1';
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wait until falling_edge(CLK);
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for i in 0 to writes loop -- Writing loop for data values
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if O_Ready = '0' then
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wait on O_Ready until O_Ready = '1';
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wait until falling_edge(CLK);
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end if;
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I_Data <= std_logic_vector(to_unsigned(i, K_Width)); -- Data to be written
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I_Valid <= '1';
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wait until falling_edge(CLK);
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I_Valid <= '0'; -- Reset 'valid' after writing
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for j in 1 to write_delay loop
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wait until falling_edge(CLK); -- Wait based on the set wait time
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end loop;
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end loop;
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I_WriteCE <= '0'; -- Deactivate write signal after writing
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wait;
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end process;
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-- Read process adapted for the falling edge of the clock signal
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read_process : process
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begin
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wait for 110 ns; -- Delay to start writing
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I_ReadCE <= '1';
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while true loop
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if O_Valid = '1' and I_Ready = '0' then
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I_Ready <= '1'; -- Signal readiness to read
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wait until falling_edge(CLK);
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if read_delay /= 0 then
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I_Ready <= '0'; -- Reset the signal after reading
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end if;
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for j in 1 to read_delay loop
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wait until falling_edge(CLK); -- Wait based on the set wait time
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end loop;
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else
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wait until falling_edge(CLK); -- Synchronize with the clock when not ready to read
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end if;
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end loop;
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end process;
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end architecture behavior;
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134
tests/Pipeline_tb.wcfg
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134
tests/Pipeline_tb.wcfg
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="./isim.wdb" id="1" type="auto">
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<top_modules>
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<top_module name="glbl" />
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<top_module name="math_real" />
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<top_module name="numeric_std" />
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<top_module name="pipeline_tb" />
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<top_module name="std_logic_1164" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<WVObjectSize size="11" />
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<wvobject fp_name="/pipeline_tb/clk" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/rst" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">rst</obj_property>
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<obj_property name="ObjectShortName">rst</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/i_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">i_data[31:0]</obj_property>
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<obj_property name="ObjectShortName">i_data[31:0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/i_valid" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">i_valid</obj_property>
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<obj_property name="ObjectShortName">i_valid</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/o_ready" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">o_ready</obj_property>
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<obj_property name="ObjectShortName">o_ready</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/o_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">o_data[31:0]</obj_property>
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<obj_property name="ObjectShortName">o_data[31:0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/o_valid" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">o_valid</obj_property>
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<obj_property name="ObjectShortName">o_valid</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/i_ready" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">i_ready</obj_property>
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<obj_property name="ObjectShortName">i_ready</obj_property>
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</wvobject>
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<wvobject fp_name="divider56" type="divider">
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<obj_property name="label">Pipeline</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<obj_property name="BkColor">128 128 255</obj_property>
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<obj_property name="TextColor">230 230 230</obj_property>
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</wvobject>
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<wvobject fp_name="group61" type="group">
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<obj_property name="label">Controller</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<wvobject fp_name="/pipeline_tb/uut0/o_enable" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">o_enable</obj_property>
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<obj_property name="ObjectShortName">o_enable</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut0/i_valid" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">i_valid</obj_property>
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<obj_property name="ObjectShortName">i_valid</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut0/o_ready" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">o_ready</obj_property>
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<obj_property name="ObjectShortName">o_ready</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut0/r_valid" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">r_valid[2:0]</obj_property>
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<obj_property name="ObjectShortName">r_valid[2:0]</obj_property>
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<obj_property name="Radix">BINARYRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut0/o_valid" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">o_valid</obj_property>
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<obj_property name="ObjectShortName">o_valid</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut0/i_ready" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">i_ready</obj_property>
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<obj_property name="ObjectShortName">i_ready</obj_property>
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</wvobject>
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<wvobject fp_name="divider39" type="divider">
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<obj_property name="label">Combinatoric</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<obj_property name="BkColor">128 128 255</obj_property>
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<obj_property name="TextColor">230 230 230</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut0/c_ready" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">c_ready</obj_property>
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<obj_property name="ObjectShortName">c_ready</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="group67" type="group">
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<obj_property name="label">Register</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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<wvobject fp_name="/pipeline_tb/uut1/i_enable" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">i_enable</obj_property>
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<obj_property name="ObjectShortName">i_enable</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut1/i_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">i_data[31:0]</obj_property>
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<obj_property name="ObjectShortName">i_data[31:0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut1/r_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">r_data[0:2]</obj_property>
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<obj_property name="ObjectShortName">r_data[0:2]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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<wvobject fp_name="/pipeline_tb/uut1/r_data[0]" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">[0]</obj_property>
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<obj_property name="ObjectShortName">r_data[0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut1/r_data[1]" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">[1]</obj_property>
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<obj_property name="ObjectShortName">r_data[1]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut1/r_data[2]" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">[2]</obj_property>
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<obj_property name="ObjectShortName">r_data[2]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="/pipeline_tb/uut1/o_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">o_data[31:0]</obj_property>
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<obj_property name="ObjectShortName">o_data[31:0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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</wvobject>
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</wave_config>
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