Introduced a new UCF file specifying pin assignments, timing constraints, and net attributes for various components of the DEPP interface and system clock. This includes location constraints for the CLK signal, the eight Dout and Din signals, and DEPP control signals, with additional setup for a 50 MHz clock signal. Defines DEPP bus signal locations and applies CLOCK_DEDICATED_ROUTE settings to relevant nets, which ensures the FPGA's resources are mapped correctly, aligning with the required hardware configuration for optimal signal integrity and timing performance.
- Set the project name to DEPP for default module and UCF file naming.
- Define target device as 'xc3s1200e-4-fg320' for the build process.
- Specify the custom UCF file location under `code/DEPP.ucf`.
- Add VHD source file 'DEPP.vhd' to the compilation sources list.
- Select 'digilent' as the programmer tool and configure associated device and index settings for JTAG and flash.
