Refined the Makefile to accommodate pre-programming commands with `PROGRAMMER_PRE` variable and introduced a specific index for flashing with Digilent devices using `DJTG_FLASH_INDEX`. This allows for more flexible configuration pre-programming hooks and coherent handling of different indices for programming and flashing operations.
The README has been updated for clarity and to reflect new options. Simplified the installation instructions for GNU Make, enriched the project configuration section with default values for build options, introduced library naming for Verilog sources, and added a section detailing console output for easy report access post-build. Additionally, documented the new `make flash` target for Digilent programmers and the placeholder for `PROGRAMMER_PRE`.
Improved the structure and readability of the README file by converting headers to markdown syntax and organizing content into clearly defined sections. Added acknowledgment for the original project and contributor. Extended installation instructions for GNU Make on various operating systems, including the Windows Subsystem for Linux. Clarified the configuration steps for creating a project and streamlined the documentation for setting up different programming utilities. Removed unimplemented features and targets sections, indicating they are work in progress or encouraging pull requests.
Updated Makefile to include detailed placement and routing by adding the `-detail` flag to PAR_OPTS. Also increased verbosity levels for tracing by setting TRACE_OPTS to `-v 3 -n 3`, providing more comprehensive diagnostic information during builds.
Refactored the Makefile to allow for dynamic library and filepath resolutions for VHDL and Verilog sources, promoting a more modular project structure. Removed hardcoded library names and filepaths, and replaced them with a mechanism that processes source file definitions, supporting a colon-separated format for specifying libraries and paths.
- Simplified RUN command echo statements for clarity.
- Established functions to process VHDL and Verilog sources, handling omitted library paths and defaults to 'work'.
- Updated build rules to utilize new lists of processed source paths and libraries.
- Included generation of detailed synthesis, map, PAR, pinout, and timing summary reports after relevant build steps for enhanced build insight.
- Modified programming commands to ensure automation without manual intervention by using `sudo` and automating confirmation prompts where applicable.
- Added a new 'flash' target for the Digilent programmer, enabling FPGA flash memory programming.
