Refactored the Makefile to allow for dynamic library and filepath resolutions for VHDL and Verilog sources, promoting a more modular project structure. Removed hardcoded library names and filepaths, and replaced them with a mechanism that processes source file definitions, supporting a colon-separated format for specifying libraries and paths.
- Simplified RUN command echo statements for clarity.
- Established functions to process VHDL and Verilog sources, handling omitted library paths and defaults to 'work'.
- Updated build rules to utilize new lists of processed source paths and libraries.
- Included generation of detailed synthesis, map, PAR, pinout, and timing summary reports after relevant build steps for enhanced build insight.
- Modified programming commands to ensure automation without manual intervention by using `sudo` and automating confirmation prompts where applicable.
- Added a new 'flash' target for the Digilent programmer, enabling FPGA flash memory programming.
