Max P
a73f125357
Renames and restructures VGA timing generator for clarity and modularity. Introduces VGA modes package for centralized resolution and timing configuration. Updates related testbenches and constraints to align with new structure. Improves maintainability and flexibility for future VGA mode additions.
94 lines
3.0 KiB
VHDL
94 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.VGA_Modes_Pkg.all;
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entity XY_Generator is
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generic (
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--@ VGA Mode (0-9) from VGA_Modes_Pkg
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G_VGA_Mode : integer := 2
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);
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port (
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--@ Clock; (**Rising edge** triggered)
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I_CLK : in std_logic;
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--@ Clock Enable; (**Synchronous**, **Active high**)
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I_CE : in std_logic;
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--@ Reset; (**Synchronous**, **Active high**)
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I_RST : in std_logic;
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--@ @virtualbus Y @dir Out Output of the Y positions, with priority over X
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O_Y_Valid : out std_logic;
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I_Y_Ready : in std_logic;
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O_Y : out std_logic_vector(K_VGA_Modes(G_VGA_Mode).Y_Width - 1 downto 0);
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--@ @end
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--@ @virtualbus Y @dir Out Output of the X positions
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O_X_Valid : out std_logic;
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I_X_Ready : in std_logic;
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O_X : out std_logic_vector(K_VGA_Modes(G_VGA_Mode).X_Width - 1 downto 0)
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--@ @end
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);
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end entity XY_Generator;
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architecture RTL of XY_Generator is
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constant K_X : integer := K_VGA_Modes(G_VGA_Mode).X_Resolution;
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constant K_Y : integer := K_VGA_Modes(G_VGA_Mode).Y_Resolution;
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signal R_X_Counter : unsigned(K_VGA_Modes(G_VGA_Mode).X_Width - 1 downto 0) := (others => '0');
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signal R_Y_Counter : unsigned(K_VGA_Modes(G_VGA_Mode).Y_Width - 1 downto 0) := (others => '0');
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signal R_Y_Valid : std_logic := '1';
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signal R_X_Valid : std_logic := '1';
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signal C_X_Valid : std_logic := '0';
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begin
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C_X_Valid <= R_X_Valid and not R_Y_Valid;
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process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_RST = '1' then
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R_X_Counter <= (others => '0');
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R_Y_Counter <= (others => '0');
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R_Y_Valid <= '1';
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R_X_Valid <= '1';
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elsif I_CE = '1' then
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if R_Y_Valid = '1' then
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if I_Y_Ready = '1' then
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R_Y_Valid <= '0';
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end if;
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elsif R_X_Valid = '1' then
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if I_X_Ready = '1' then
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R_X_Valid <= '0';
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end if;
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else
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if R_X_Counter = (K_X - 1) then
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R_X_Counter <= (others => '0');
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R_X_Valid <= '1';
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if R_Y_Counter = (K_Y - 1) then
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R_Y_Counter <= (others => '0');
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R_Y_Valid <= '1';
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else
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R_Y_Counter <= R_Y_Counter + 1;
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R_Y_Valid <= '1';
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end if;
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else
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R_X_Counter <= R_X_Counter + 1;
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R_X_Valid <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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O_X <= std_logic_vector(R_X_Counter);
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O_Y <= std_logic_vector(R_Y_Counter);
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O_Y_Valid <= R_Y_Valid;
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O_X_Valid <= C_X_Valid;
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end architecture;
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