Max P a73f125357 Refactors VGA timing and mode handling ...

Renames and restructures VGA timing generator for clarity and modularity.
Introduces VGA modes package for centralized resolution and timing configuration.
Updates related testbenches and constraints to align with new structure.
Improves maintainability and flexibility for future VGA mode additions.

2025-04-26 10:26:52 +00:00

build @ d1a3b7cec9

Refactors VGA timing and mode handling

2025-04-26 10:26:52 +00:00

src

Refactors VGA timing and mode handling

2025-04-26 10:26:52 +00:00

tests

Refactors VGA timing and mode handling

2025-04-26 10:26:52 +00:00

.gitignore

Add .gitignore to exclude locale files

2025-03-27 15:59:31 +00:00

.gitmodules

Add submodule for Xilinx ISE Makefile

2025-03-27 15:59:05 +00:00

project.cfg

Refactors VGA timing and mode handling

2025-04-26 10:26:52 +00:00

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60 KiB

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VHDL 100%