HDL/VGA
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
15 Commits 1 Branch 0 Tags
1ab18cda839f465f230a5ec870252e2004906d77
Commit Graph

1 Commits

Author SHA1 Message Date
Max P
1011989322 Adds project configuration file for VGA design with Xilinx ISE settings 2025-04-27 19:27:56 +00:00