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Test @ 640x480

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This commit is contained in:
0xMax42
2025-03-27 16:01:32 +00:00
parent c449016835
commit cd6524c62e
1 changed files with 4 additions and 15 deletions
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19
src/VGATimingGenerator_test.vhd
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@@ -27,11 +27,11 @@ end entity VGATimingGenerator_test;
architecture RTL of VGATimingGenerator_test is architecture RTL of VGATimingGenerator_test is
signal R_PixelReady : std_logic_vector(1 downto 0); signal R_PixelReady : std_logic_vector(1 downto 0);
signal R_LineCounter : unsigned(19 downto 0) := (others => '0'); signal R_LineCounter : unsigned(19 downto 0) := (others => '0');
signal R_VSync : std_logic; signal R_VSync : std_logic;
signal CLK_FB : std_logic; signal CLK_FB : std_logic;
signal PixelCLK : std_logic; signal PixelCLK : std_logic;
begin begin
@@ -54,13 +54,13 @@ begin
port map port map
( (
CLK0 => CLK_FB, CLK0 => CLK_FB,
CLKFX => PixelCLK, CLKDV => PixelCLK,
CLKFB => CLK_FB, CLKFB => CLK_FB,
CLKIN => I_CLK CLKIN => I_CLK
); );
VGAColorGenerator : process (PixelCLK) VGAColorGenerator : process (PixelCLK)
variable R_SignalCounter : unsigned(3 downto 0) := (others => '0'); variable R_SignalCounter : unsigned(3 downto 0) := (others => '0');
begin begin
if rising_edge(PixelCLK) then if rising_edge(PixelCLK) then
if R_VSync = '0' then if R_VSync = '0' then
@@ -110,17 +110,6 @@ begin
end process; end process;
VGATimingGenerator : entity work.VGATimingGenerator VGATimingGenerator : entity work.VGATimingGenerator
generic map(
G_HFront => 88,
G_HSync => 44,
G_HBack => 148,
G_HTotal => 2200,
G_VFront => 4,
G_VSync => 5,
G_VBack => 36,
G_VTotal => 1125
)
port map port map
( (
I_CLK => PixelCLK, I_CLK => PixelCLK,